MAXQ3181-RAN+ datasheet(15/84 Pages) MAXIM

15 / 84 page

Low-Power, Active Energy, Polyphase AFE

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tPOR

VRST1

BROWNOUT DETECTION

BROWNOUT DETECTION (ALWAYS

ENABLED OUTSIDE OF STOP MODE)

FORCES RESET STATE. POR = 1

BROWNOUT DETECTION DISABLED

DURING STOP MODE.

NO RESET IS GENERATED.

BROWNOUT DETECTION DISABLED.

POR LEVEL CAUSES RESET.

VPOR

INTERNAL

RESET

STOP MODE

Figure 2. Brownout Reset

to 0, meaning that the MAXQ3181 always switches to

the high-frequency clock before it begins accepting

commands in Initialization Mode.

When an external reset occurs from Stop Mode, execu-

tion (in Initialization Mode) resumes after 128 cycles of

the internal RC oscillator (or approximately 128μs).

Power-On Reset

When the MAXQ3181 is first powered up, or when the

power supply, VDVDD, drops below the VRST power-fail

trip point (outside of Stop Mode), the MAXQ3181 is

held in power-on reset. Once the power supply rises

above the VRST level, the power-on reset state is

released and all registers are reset to their defaults and

execution resumes in Initialization Mode. The high-fre-

quency external crystal (LOWPM = 0) is always select-

ed as the clock source following any power-on or

brownout reset.

In Stop Mode brownout detection is disabled, so a

power-on reset does not occur until VDVDD drops to a

lower level (VPOR). From the master’s perspective,

power-on resets and brownout resets both cause the

MAXQ3181 to reset in the same way.

Watchdog Reset

The MAXQ3181 includes a hardware watchdog timer

that is armed and periodically reset automatically dur-

ing normal operation. Under normal circumstances, the

MAXQ3181 always resets the watchdog timer often

enough to prevent it from expiring. However, if an inter-

nal error of some kind causes the MAXQ3181 to lock up

or enter an endless execution loop, the watchdog timer

expires and triggers an automatic hardware reset.

There is no register flag to indicate to the master that a

watchdog reset has occurred, but the RESET line

strobes low briefly.

The watchdog timer does not run during Stop Mode.

Software Reset

The master initiates a software reset by setting the

SWRES (OPMODE0.3) bit to 1. When a software reset

occurs, the MAXQ3181 clears all registers to their

default states and returns to Initialization Mode, in the

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