MAXQ3181-RAN+ datasheet(31/84 Pages) MAXIM

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Low-Power, Active Energy, Polyphase AFE

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The interrupt request flag register contains bits that indicate the reason the IRQ pin has become active. The active

bit must be cleared by the host to avoid continuing firing of the interrupt by the MAXQ3181.

BIT

NAME

FUNCTION

DSPOR

When set, the DSP was unable to complete processing one cycle when another cycle was due to

begin. This indicates that the R_ADCRATE is set too low, and that samples are arriving more quickly

than they can be processed. Increase the value of the R_ADCRATE register to reduce the load on the

DSP.

DSPRDY

When set, the latest DSP cycle has just completed.

13, 7:3

—

Reserved.

DCHA

When set, the direction of real energy flow has changed (that is, from toward the load to away from the

load, or from away from the load to toward the load).

NOZX

When set, the MAXQ3181 has failed to detect zero crossings on one or more voltage channels for the

time defined by the NZX_TIMO register.

When set, the absolute instantaneous voltage level in one or more voltage channels failed to exceed

the trip level set in the UVLVL (Undervoltage Level) register for one DSP cycle.

When set, the absolute instantaneous voltage level in one or more voltage channels has exceeded the

trip level set in the OVLVL (Overvoltage Level) register.

When set, the absolute instantaneous current in one or more current channels has exceeded the trip

level set in the OCLVL (Overcurrent Level) register.

EOVF

When set, one or more energy accumulators have an MSB overflow condition.

CHSCH

When set, indicates a change of the CHKSUM. The CHKSUM is computed over the configuration and

calibration data. The host should review a change in CHKSUM because any change in the

configuration or calibration data affects the metering operation and accuracy.

PWRF

When set, a power-supply failure is imminent and the supervisory processor should begin taking steps

to save its state and prepare for a loss of power.

Global Interrupt Registers

Interrupt Request Flag Register (IRQ_FLAG) (0x004)

Bit:

Name:

DSPOR

DSPRDY

—

DCHA

NOZX

Reset:

Bit:

Name:

—

EOVF

CHSCH

PWRF

Reset:

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