DM9102DEP datasheet(38/70 Pages) DAVICOM

38 / 70 page

Final

Version: DM9102D-DS-F01

May 10, 2006

SLEEP

0,RW

Sleep Mode:

Writing a 1 to this bit will cause PHY entering the Sleep mode and power

down all circuit except oscillator and clock generator circuit. When waking up

from Sleep mode (write this bit to 0), the configuration will go back to the state

before sleep; but the state machine will be reset.

RLOUT

0,RW

Remote Loop out Control:

When this bit is set to 1, the received data will loop out to the transmit channel.

This is useful for testing bit error rate.

6.3.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H

Bit

Name

Default

Description

100FDX

1, RO

100M Full Duplex Operation Mode:

After Auto-negotiation is completed, results will be written to this bit. If this bit is

1, it means the operation mode is a 100Mbps Full Duplex mode. The software

can read bit[15:12] to see which mode is selected after Auto-negotiation. This

bit is invalid when it is not in the Auto-negotiation mode.

100HDX

1, RO

100M Half Duplex Operation Mode:

After Auto-negotiation is completed, results will be written to this bit. If this bit is

1, it means the operation mode is a 100Mbps Half Duplex mode. The

software can read bit[15:12] to see which mode is selected after

Auto-negotiation. This bit is invalid when it is not in the Auto-negotiation mode.

10FDX

1, RO

10M Full Duplex Operation Mode:

After Auto-negotiation is completed, results will be written to this bit. If this bit is

1, it means the operation mode is a 10Mbps Full Duplex mode. The software

can read bit[15:12] to see which mode is selected after Auto-negotiation. This

bit is invalid when it is not in the Auto-negotiation mode.

10HDX

1, RO

10M Half Duplex Operation Mode:

After Auto-negotiation is completed, results will be written to this bit. If this bit is

1, it means the operation mode is a 10Mbps Half Duplex mode. The software

can read bit[15:12] to see which mode is selected after Auto-negotiation. This

bit is invalid when it is not in the Auto-negotiation mode.

11:10

Reserved

00, RO

Reserved:

Reserved

1, RW

Reserved:

Write as 0, ignore on read

8:4

PHYAD[4:0]

00001, RW PHY Address Bit 4:0

3:0

ANMB[3:0]

0000, RO Auto-negotiation Monitor Bits:

These bits are for debug only. The Auto-negotiation status will be written to

these bits.

DM9102DEP 데이터시트(PDF) 38 Page - Davicom Semiconductor, Inc.

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