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DM9102DEP 데이터시트(PDF) 31 Page - Davicom Semiconductor, Inc.

부품명 DM9102DEP
상세설명  Single Chip Fast Ethernet NIC Controller
PDF  70 Pages
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제조업체  DAVICOM [Davicom Semiconductor, Inc.]
홈페이지  http://www.davicom.com.tw
Logo DAVICOM - Davicom Semiconductor, Inc.

DM9102DEP 데이터시트(HTML) 31 Page - Davicom Semiconductor, Inc.

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Final
31
Version: DM9102D-DS-F01
May 10, 2006
6.2.12 Sample Frame Access Register (CR13) (reference to section 7.5 Power Management)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
98
7
6
5
4
3
2
1
0
Register
General definition
bit8 ~ 3
R/W
TxFIFO
Transmit FIFO access port
32H
R/W
RxFIFO
Receive FIFO access port
35H
R/W
DiagReset General reset for diagnostic pointer port
38H
W
6.2.13 Sample Frame Data Register (CR14) (reference to section 7.5 Power Management)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
98
7
6
5
4
3
2
1
0
6.2.14 Watchdog and Jabber Timer Register (CR15)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
98
7
6
5
4
3
2
1
0
Bit
Name
Default
Description
31
TXSUMC
0,WO
in transmit, generate IP/TCP/UDP chksum depend-on TX desc. control
30
IPSUM
0,WO
in transmit, generate IP chksum to all packets
29
TCPSUM
0,WO
in transmit, generate TCP chksum to all packets
28
UDPSUM
0,WO
in transmit, generate UDP chksum to all packets
27
RXSUM
0,WO
In receiving, report IP/TCP/UDP checksum status to RDES0
26:15
Reserved
0,RO
Reserved
14
TXP0
0,RW
Transmit pause packet
Set to transmit pause packet with pause timer = 0000h, this bit will be cleared if the
pause packet had transmitted.
13
TXPF
0,RW
Transmit pause packet
Set to transmit pause packet with pause timer = FFFFh, this bit will be cleared if the
pause packet had transmitted.
12:11
Reserved
0,RO
Reserved
10
FLCE
0,RW
Flow Control Enable
Set to enable the decode of the pause packet.
9
RXPS
0,R/C
The latched status of the decode of the pause packet.
8
Reserved
0,RO
Reserved.
7
RXPCS
0,RO
It is set to indicate that the current pause timer of pause packet is not down count to
zero yet.
6
VLAN
0,RW
VLAN length Capability Enable
It is set to enable the VLAN length mode and will not report the frame_too_long bit
status to RDES0 if receive packet size under 1526-byte.



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