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DM9102DEP 데이터시트(PDF) 20 Page - Davicom Semiconductor, Inc. |
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DM9102DEP 데이터시트(HTML) 20 Page - Davicom Semiconductor, Inc. |
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20 / 70 page ![]() 20 Final Version: DM9102D-DS-F01 May 10, 2006 6.1.13 Power Management Control/Status (xxxxxx54H~PMCSR) Reserved 31 R/W Reserved R/W Reserved R/W 16 15 14 9 8 7 2 1 0 PME_Status PME_En Power_State Bit Default Type Description 31:16 0000H RO Reserved 15 0 RW/C PME_ Status This bit is set when the function would normally assert the PME# signal independent of the state of the PME_ En bit. Writing a “1” to this bit will clear it. This bit defaults to “0” if the function does not support PME# generation from D3 (cold).If the function supports PME# from D3 (cold) then this bit is sticky and must be explicitly cleared by the operating system whenever the operating system is initially loaded. 14:9 000000 RO Reserved It means that the DM9102D does not support reporting power consumption. 8 1 RW PME_ En Write “1” to enables the function to assert PME#, write “0” to disable PME# assertion This bit defaults to “0” if the function does not support PME# generation from D3 (cold) If the function supports PME# from D3(cold) then this bit is sticky and must be explicitly cleared by the operating system each time the operating system is initially loaded. 7:2 000000 RO Reserved 1:0 00 RW This two bits field is both used to determine the current power state of a function and to set the function into a new power state. The definitions given below 00: D0 11: D3 (hot) |
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