LM4549B datasheet(20/28 Pages) NSC

20 / 28 page

AC Link Serial Interface Protocol

(Continued)

check the status of these subsections after Initialization,

Cold Reset, or the use of the powerdown modes in order to

minimize the risk of distorting analog signals passed before

the subsections are ready.

The 4 bits 14, 13, 12 and 11 indicate that the data in slots 1,

2, 3 and 4, respectively, are valid.

SLOT 0, INPUT FRAME

Bit

Description

Comment

Codec Ready

Bit

1 = AC Link Interface Ready

Slot 1 data

valid

1 = Valid Status Address or

Slot Request

Slot 2 data

valid

1 = Valid Status Data

Slot 3 data

valid

1 = Valid PCM Data

(Left ADC)

Slot 4 data

valid

1 = Valid PCM Data

(Right ADC)

SDATA_IN: Slot 1 – Status Address / Slot Request Bits

This slot echoes (in bits 18 – 12) the 7-bit address of the

codec control/status register received from the controller as

part of a read-request in the previous frame. If no read-

request was received, the codec stuffs these bits with zeros.

Bits 11, 10 are Slot Request bits that support the Variable

Rate Audio (VRA) capabilities of the LM4549B. For all codec

Primary and Secondary modes, the left and right channels of

the DAC take PCM data from slots 3 and 4 in the Output

Frame respectively. The codec uses bits 11 and 10 to re-

quest DAC data from these two slots. If bits 11 and 10 are set

to 0, the controller should respond with valid PCM data in

slots 3 and 4 of the next Output Frame. If bits 11 and 10 are

set to 1, the controller should not send data.

The codec has full control of the slot request bits. By default,

data is requested in every frame, corresponding to a sample

rate equal to the frame rate (SYNC frequency) – 48 kHz

when XTAL_IN = 24.576 MHz. To send samples at a rate

below the frame rate, a controller should set VRA = 1 (bit 0

in the Extended Audio Control/Status register, 2Ah) and

program the desired rate into the PCM DAC Rate register,

2Ch. Both DAC channels operate at the same sample rate.

Values for common sample rates are given in the Register

Description section (Sample Rate Control Registers, 2Ch,

32h) but any rate between 4 kHz and 48 kHz (to a resolution

of 1 Hz) is supported. Slot Requests from the LM4549B are

issued completely deterministically. For example if a sample

rate of 8000 Hz is programmed into 2Ch then the LM4549B

will always issue a slot request in every sixth frame. A

frequency of 9600 Hz will result in a request every fifth frame

while a frequency of 8800 Hz will cause slot requests to be

spaced alternately five and six frames apart. This determin-

ism makes it easy to plan task scheduling on a system

controller and simplifies application software development.

The LM4549B will ignore data in Output Frame slots that do

not follow an Input Frame with a Slot Request. For example,

if the LM4549B is expecting data at a 8000 Hz rate yet the

AC ’97 Digital Audio Controller continues to send data at

48000 Hz, then only those one-in-six audio samples that

follow a Slot Request will be used by the DAC. The rest will

be discarded.

Bits 9 – 2 are request bits for slots not used by the LM4549B

and are stuffed with zeros. Bits 1 and 0 are reserved and are

also stuffed with zeros.

SLOT 1, INPUT FRAME

Bits

Description

Comment

Reserved

Stuffed with "0" by LM4549B

18:12

Status Register

Index

Echo of the requested Status

Slot 3 Request

bit

(For left DAC

PCM data)

0 = Controller should send

valid data in Slot 3 of the

next Output Frame.

1 = Controller should not

send Slot 3 data.

Slot 4 Request

bit

(For right DAC

PCM data)

0 = Controller should send

valid data in Slot 4 of the

next Output Frame.

1 = Controller should not

send Slot 4 data.

9:2

Unused Slot

Request bits

Stuffed with "0"s by LM4549B

1,0

Reserved

Stuffed with "0"s by LM4549B

SDATA_IN: Slot 2 – Status Data

This slot returns 16-bit status data read from a codec control/

status register. The codec sends the data in the frame fol-

lowing a read-request by the controller (bit 15, slot 1 of the

Output Frame). If no read-request was made in the previous

frame the codec will stuff this slot with zeros.

SLOT 2, INPUT FRAME

Bits

Description

Comment

19:4

Status Data

Data read from a codec

control/status register.

Stuffed with “0”s if no

read-request in previous frame.

3:0

Reserved

Stuffed with "0"s by LM4549B

SDATA_IN: Slot 3 – PCM Record Left Channel

This slot contains sampled data from the left channel of the

stereo ADC. The signal to be digitized is selected using the

Record Select register (1Ah) and subsequently routed

through the Record Select Mux and the Record Gain ampli-

fier to the ADC.

This is a 20-bit slot and the digitized 18-bit PCM data is

transmitted in an MSB justified format. The remaining 2

LSBs are stuffed with zeros.

SLOT 3, INPUT FRAME

Bits

Description

Comment

19:2

PCM Record

Left Channel

data

18-bit PCM sample from left

ADC

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