LM4549B datasheet(25/28 Pages) NSC

25 / 28 page

Low Power Modes (Continued)

Improving System Performance

The audio codec is capable of dynamic range performance

in excess of 90 db., but the user must pay careful attention to

several factors to achieve this. A primary consideration is

keeping analog and digital grounds separate, and connect-

ing them together in only one place. Some designers show

the connection as a zero ohm resistor, which allows naming

the nets separately. Although it is possible to use a two layer

board, it is recommended that a minimum of four layers be

used, with the two inside layers being analog ground and

digital ground. If EMI is a system consideration, then as

many as eight layers have been successfully used. The 12

and 25 MHz. clocks can have significant harmonic content

depending on the rise and fall times. Bypass capacitors

should be very close to the package. The analog VDD pins

should be supplied from a separate regulator to reduce

noise. By operating the digital portion on 3.3V instead of 5V,

an additional 0.5-0.7 db improvement can be obtained.

The bandgap reference and the anti-pop slow turn-on circuit

were improved in the LM4549B. A pullup resistor is not

required on V

REF, pin 27. For an existing design, the 10 k

Ω

resistor can be left on the pc board, but the temperature

coefficient will improve with no resistor on this pin. In addi-

tion, the THD will improve by 0.2–0.5 dB. The external

capacitor is charged by an internal current source, ramping

the voltage slowly. This results in slow turn-on of the audio

stages, eliminating “pops and clicks”. Thus, turn-on perfor-

mance is also improved. The pullup resistor, in conjunction

with the internal impedance and the external capacitor, form

a frequency dependent divider from the analog supply. Noise

on the analog supply will be coupled into the audio path, with

approximately 30 dB. of attenuation. Although this is not a

large amount if the noise on the supply is tens of millivolts, it

will prevent SNR from exceeding 80 dB.

In Figure 1 and Figure 2, the input coupling capacitors are

shown as 1 µF capacitors. This is only necessary for extend-

ing the response down to 20 Hz. for music applications. For

telematics or voice applications, thelower 3 dB. point can be

much higher. Using a guaranteed input resistance of 10 k

Ω,

(40 k

Ω typical), a 0.1 µF capacitor may be used. The lower 3

dB point will still be below 300 Hz. By using a smaller

capacitor, the package size may be reduced, leading to a

lower system cost.

Backwards Compatibility

The LM4549B is improved compared with the LM4549A. If it

is required to build a board that will use either part, a 10 k

Ω

resistor must be added from the V

REF pin (pin 27) to AVDD for

the LM4549A. It is not required for the LM4549B. Addition of

this resistor will slightly increase the temperature coefficient

of the internal bandgap reference and decrease the THD

performance, but overall performance will still be better than

the LM4549A. The LM4549A requires that pins 1 and 9

(DV

DD) connect directly to a 27 nH. inductor before going to

the 3.3 Volt digital supply and the bypass capacitors. The

inductor is not required for the LM4549B and should not be

used.

Multiple Codecs

EXTENDED AC LINK

Up to four codecs can be supported on the extended AC

Link. These multiple codec implementations should run off a

common BIT_CLK generated by the Primary Codec. All

codecs share the AC ’97 Digital Controller output signals,

SYNC, SDATA_OUT, and RESET#. Each codec, however,

supplies its own SDATA_IN signal back to the controller, with

the result that the controller requires one dedicated input pin

per codec. (Figure 9).

By definition there can be one Primary Codec and up to

three Secondary Codecs on an extended AC Link. The

Primary Codec has a Codec Identity = (ID1, ID0) = ID = 00

while Secondary Codecs may have identities equal to 01, 10

or 11. The Codec Identity is used as a chip select function.

This allows the Command and Status registers in any of the

codecs to be individually addressed although the access

mechanism for Secondary Codecs differs slightly from that

for a Primary.

The Identity control pins, ID1#, ID0# (pins 46 and 45) are

internally pulled up to DV

DD. The Codec may therefore be

20123509

FIGURE 8. AC Link Powerdown Timing

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