ANALOG I/O (Continued)

Name

Pin

I / O

Functional Description

LNLVL_OUT_L

39

O

Left Stereo Channel Output

This line level output (1 Vrms nominal) is fed from the left channel of the Stereo Mix signal

from MIX2 via the Line Level Volume register, 04h. The LNLVL_OUT_L amplitude can be

muted (along with LNLVL_OUT_R) or adjusted from 0 dB to - 46.5 dB in 1.5 dB steps

LNLVL_OUT_R

41

O

Right Stereo Channel Output

This line level output (1 Vrms nominal) is fed from the right channel of the Stereo Mix signal

from MIX2 via the Line Level Volume register, 04h. The LNLVL_OUT_R amplitude can be

muted (along with LNLVL_OUT_L) or adjusted from 0 dB to - 46.5 dB in 1.5 dB steps

DIGITAL I/O AND CLOCKING

Name

Pin

I / O

Functional Description

XTL_IN

2

I

24.576 MHz crystal or oscillator input

To complete the oscillator circuit use a fundamental mode crystal operating in parallel

resonance and connect a 1M

Ω resistor across pins 2 and 3. Choose the load capacitors

(Figure 2, C1, C2) to suit the crystal (e.g. C1 = C2 = 33 pF for a crystal designed for a 20 pF

load. Assumes that each ’Input + trace’ capacitance=7pF)

This pin may also be used as the input for an external oscillator (24.576 MHz nominal) at

standard logic levels (V

This pin is only used when the codec is in Primary mode. It may be left open (NC) for any

Secondary mode.

XTL_OUT

3

O

24.576 MHz crystal output

Used with XTAL_IN to configure a crystal oscillator.

When the codec is used with an external oscillator this pin should be left open (NC).

When the codec is configured in a Secondary mode this pin is not used and may be left open

(NC).

SDATA_OUT

5

I

Input to codec

This is the input for AC Link Output Frames from an AC ’97 Digital Audio Controller to the

LM4549B codec. These frames can contain both control data and DAC PCM audio data. This

input is sampled by the LM4549B on the falling edge of BIT_CLK.

BIT_CLK

6

I/O

AC Link clock

An OUTPUT when in Primary Codec mode. This pin provides a 12.288 MHz clock for the AC

Link. The clock is derived (internally divided by two) from the 24.576 MHz signal at the crystal

input (XTL_IN).

This pin is an INPUT when the codec is configured in any of the Secondary Codec modes

and would normally use the AC Link clock generated by a Primary Codec.

SDATA_IN

8

O

Output from codec

This is the output for AC Link Input Frames from the LM4549B codec to an AC ’97 Digital

Audio Controller. These frames can contain both codec status data and PCM audio data from

the ADCs. The LM4549B clocks data from this output on the rising edge of BIT_CLK.

SYNC

10

I

AC Link frame marker and Warm Reset

This input defines the boundaries of AC Link frames. Each frame lasts 256 periods of

BIT_CLK. In normal operation SYNC is a 48 kHz positive pulse with a duty cycle of 6.25%

(16/256). SYNC is sampled on the falling edge of BIT_CLK and the codec takes the first

positive sample of SYNC as defining the start of a new AC Link frame. If a subsequent SYNC

pulse occurs within 255 BIT_CLK periods of the frame start it will be ignored.

SYNC is also used as an active high input to perform an (asynchronous) Warm Reset. Warm

Reset is used to clear a power down state on the codec AC Link interface.

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