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LM4549B 데이터시트(PDF) 4 Page - National Semiconductor (TI) |
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LM4549B 데이터시트(HTML) 4 Page - National Semiconductor (TI) |
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4 / 28 page ![]() Electrical Characteristics (Notes 1, 5) The following specifications apply for AV DD = 5V, DVDD = 3.3V, Fs = 48 kHz, single codec configuration, (primary mode) unless otherwise noted. Limits apply for T A= 25˚C. The reference for 0 dB is 1 Vrms unless otherwise specified. (Continued) Symbol Parameter Conditions LM4549B Units (Limits) Typical (Note 6) Limit (Note 7) Analog to Digital Converters Resolution 18 Bits Dynamic Range (Note 9) -60 dB Input THD+N, A-Weighted 90 86 dB (min) Frequency Response -1 dB Bandwidth 20 kHz Digital to Analog Converters Resolution 18 Bits Dynamic Range (Note 9) -60 dB Input THD+N, A-Weighted 89 82 dB (min) THD Total Harmonic Distortion V IN =-3dB,f=1 kHz, RL =10k Ω 0.01 % Frequency Response 20 - 21 k Hz Group Delay (Note 9) Sample Frequency = 48 kHz 0.36 1 ms (max) Out of Band Energy (Note 10) -40 dB Stop Band Rejection 70 dB D T Discrete Tones -96 dB Analog Output Section A S Step Size 0 dB to -46.5 dB 1.5 dB A M Mute Attenuation 86 dB Z OUT Output Impedance (Note 9) All Analog Outputs 220 Ω Digital I/O (Note 9) V IH High level input voltage 0.65 x DV DD V (min) V IL Low level input voltage 0.35 x DV DD V (max) V OH High level output voltage I O = −2.5 mA. 0.90 x DV DD V (min) V OL Low level output voltage I O = 2.5 mA. 0.10 x DV DD V (max) I L Input Leakage Current AC Link inputs ±10 µA I L Tri state Leakage Current High impedance AC Link outputs ±10 µA C IN AC-Link I/O capacitance(Note 9) SDout, BitClk, SDin, Sync, Reset# only 4 7.5 pF (max) I DR Output drive current AC Link outputs 5 mA Digital Timing Specifications (Note 9) F BC BIT_CLK frequency 12.288 MHz T BCP BIT_CLK period 81.4 ns T CH BIT_CLK high Variation of BIT_CLK duty cycle from 50% ±20 % (max) F SYNC SYNC frequency 48 kHz T SP SYNC period 20.8 µs T SH SYNC high pulse width 1.3 µs T SL SYNC low pulse width 19.5 µs T DSETUP Setup Time for codec data input SDATA_OUT to falling edge of BIT_CLK 3.5 10 ns (min) T DHOLD Hold Time for codec data input(Note 9) Hold time of SDATA_OUT from falling edge of BIT_CLK 5.3 10 ns (min) T SSETUP Setup Time for codec SYNC input(Note 9) SYNC to falling edge of BIT_CLK 3.8 10 ns (min) www.national.com 4 |
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