LM4549B datasheet(24/28 Pages) NSC

24 / 28 page

support). VRA is indicated by a "1" in bit 0. The two MSBs,

ID1 and ID0, show the current Codec Identity as defined by

the Identity pins ID1#, ID0#. Note that the external logic

connections to ID1#, ID0# (pins 46 and 45) are inverse in

polarity to the value of the Codec Identity (ID1, ID0) held in

bits D15, D14. Codec mode selections are shown in the

table below.

Pin 46

(ID1#)

Pin 45

(ID0#)

D15,28h

(ID1)

D14,28h

(ID0)

Codec Identity

Mode

NC/DV

Primary

NC/DV

GND

Secondary 1

GND

NC/DV

Secondary 2

GND

Secondary 3

EXTENDED AUDIO STATUS/CONTROL REGISTER

(2Ah)

This read/write register provides status and control of the

variable sample rate capabilities in the LM4549B. Setting the

LSB of this register to "1" enables Variable Rate Audio (VRA)

mode and allows DAC and ADC sample rates to be pro-

grammed via registers 2Ch and 32h respectively.

BIT

Function

VRA

*0 = VRA off (Frame-rate sampling)

1 = VRA on

Default: 0000h

SAMPLE RATE CONTROL REGISTERS (2Ch, 32h)

These read/write registers are used to set the sample rate

for the left and right channels of the DAC (PCM DAC Rate,

2Ch) and the ADC (PCM ADC Rate, 32h). When Variable

Rate Audio is enabled via bit 0 of the Extended Audio

Control/Status register (2Ah), the sample rates can be pro-

grammed, in 1 Hz increments, to be any value from 4 kHz to

48 kHz. The value required is the hexadecimal representa-

tion of the desired sample rate, e.g. 8000

10 = 1F40h. Below

is a list of the most common sample rates and the corre-

sponding register (hex) values.

Common Sample Rates

SR15:SR0

Sample Rate (Hz)

1F40h

8000

2B11h

11025

3E80h

16000

5622h

22050

AC44h

44100

*BB80h

*48000

VENDOR ID REGISTERS (7Ch, 7Eh)

These two read-only (4E53h, 4349h) registers contain Na-

tional’s Vendor ID and National’s LM45xx codec version

designation. The first 24 bits (4Eh, 53h, 43h) represent the

three ASCII characters “NSC” which is National’s Vendor ID

for Microsoft’s Plug and Play. The last 8 bits are the two

binary coded decimal characters, 4, 9 and identify the codec

to be an LM4549B.

RESERVED REGISTERS

Do not write to reserved registers. In particular, do not write

to registers 24h, 5Ah, 74h and 7Ah. All registers not listed in

the LM4549B Register Map are reserved. Reserved regis-

ters will return 0000h if read.

Low Power Modes

The LM4549B provides 6 bits to control the powerdown state

of internal analog and digital subsections and clocks. It also

provides one bit intended to control an external analog

power amplifier. These 7 bits (PR0 – PR5, EAPD) are lo-

cated in the 8 MSBs of the Powerdown Control/Status reg-

ister, 26h. The status of the four main analog subsections is

given by the 4 LSBs in the same register, 26h.

The powerdown bits are implemented in compliance with AC

’97 Rev 2.1 to support the standard device power manage-

ment states D0 – D3 as defined in the ACPI and PCI Bus

Power Management Specification.

PR0 controls the powerdown state of the ADC and associ-

ated sampling rate conversion circuitry. PR1 controls power-

down for the DAC and the DAC sampling rate conversion

circuitry. PR2 powers down the mixer circuits (MIX1, MIX2,

National 3D Sound, Mono Out, Line Out). PR3 powers down

REF in addition to all the same mixer circuits as PR2. PR4

powers down the AC Link Digital Interface – see Figure 8 for

signal powerdown timing. PR5 disables internal clocks but

leaves the crystal oscillator and BIT_CLK running (needed

for minimum Primary mode powerdown dissipation in multi-

codec systems). PR6 is not used. EAPD controls the Exter-

nal Amplifier PowerDown pin (pin 47).

After a subsection has undergone a powerdown cycle, the

appropriate status bit(s) in the Powerdown Control/Status

ticular the startup time of the V

REF circuitry depends on the

value of the decoupling capacitors on pin 27 (3.3 µF, 0.1 µF

in parallel is recommended).

When the AC Link Digital Interface is powered down the

codec output signals SDATA_IN and BIT_CLK (Primary

mode) are cleared to zero and no control data can be passed

between controller and codec(s). This powerdown state can

be cleared in two ways: Cold Reset (RESET# = 0) or Warm

Reset (SYNC = 1, no BIT_CLK). Cold Reset sets all regis-

ters back to their default values (including clearing PR4)

whereas Warm Reset only clears the PR4 bit and restarts

the AC Link Digital Interface leaving all register contents

otherwise unaffected. For Warm Reset (see Timing Dia-

grams), the SYNC input is used asynchronously. The

LM4549B codec allows the AC Link digital interface power-

down state to be cleared immediately so that its duration can

be essentially as short as T

SH, the Warm Reset pulse width.

However for conformance with AC ’97 Rev 2.1, Warm Reset

should not be applied within four frame times of powerdown

i.e. the AC Link powerdown state should be allowed to last at

least 82.8 µs.

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