360J datasheet(8/68 Pages) INTEL

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Introduction

Datasheet

transfer rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver

addresses two times per bus clock and is referred to as a “double-clocked” or 2X

address bus. Working together, the 4X data bus and 2X address bus provide a data bus

bandwidth of up to 3.2 GB/second. The FSB uses Advanced Gunning Transceiver Logic

(AGTL+) signalling technology, a variant of (GTL+) signaling technology with low power

enhancements.

The Celeron M processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-

FCPGA) and surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package

technology. The Micro-FCPGA package plugs into a 479-hole, surface-mount, zero

insertion force (ZIF) socket, which is referred to as the mPGA479M socket.

1.1

Terminology

1.2

References

Material and concepts available in the following documents may be beneficial when

reading this document.

Term

Definition

A “#” symbol after a signal name refers to an active low signal, indicating a

signal is in the active state when driven to a low level. For example, when

RESET# is low, a reset has been requested. Conversely, when NMI is high,

a nonmaskable interrupt has occurred. In the case of signals where the

name does not imply an active state but describes part of a binary

sequence (such as address or data), the “#” symbol implies that the signal

is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and D[3:0]#

= “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).

XXXX means that the specification or value is yet to be determined.

Front Side Bus

(FSB)

Refers to the interface between the processor and system core logic (also

known as the chipset components).

Document

Document Location1

Intel® Celeron® M Processor Specification Update

http://www.intel.com/

design/mobile/specupdt/

300303.htm

Mobile Intel® 915PM/GM/GMS and 910GML Express Chipset

Datasheet

http://www.intel.com/

design/mobile/datashts/

305264.htm

Mobile Intel® 915PM/GM/GMS and 910GML Express Chipset

Specification Update

http://www.intel.com/

design/mobile/specupdt/

307167.htm

Intel® I/O Controller Hub 6 (ICH6) Family Datasheet

http://www.intel.com/

design/chipsets/datashts/

301473.htm

Intel® I/O Controller Hub 6 (ICH6) Family Specification Update

http://www.intel.com/

design/chipsets/specupdt/

301474.htm

Intel® 855PM Chipset Memory Controller Hub (MCH) Datasheet

http://www.intel.com/

design/chipsets/datashts/

252613.htm

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