360J datasheet(59/68 Pages) INTEL

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Datasheet

Package Mechanical Specifications and Pin Information

INIT#

Input

INIT# (Initialization), when asserted, resets integer registers inside

the processor without affecting its internal caches or floating-point

registers. The processor then begins execution at the power-on

Reset vector configured during power-on configuration. The

processor continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous signal. However, to ensure

recognition of this signal following an Input/Output Write instruction,

it must be valid along with the TRDY# assertion of the corresponding

Input/Output Write bus transaction. INIT# must connect the

appropriate pins of both FSB agents.

If INIT# is sampled active on the active to inactive transition of

RESET#, then the processor executes its Built-in Self-Test (BIST).

ITP_CLK[1:0]

Input

ITP_CLK[1:0] are copies of BCLK that are used only in processor

systems where no debug port is implemented on the system board.

ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port

implemented on an interposer. If a debug port is implemented in the

system, ITP_CLK[1:0] are no connects in the system. These are not

processor signals.

LINT[1:0]

Input

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins

of all APIC Bus agents. When the APIC is disabled, the LINT0 signal

becomes INTR, a maskable interrupt request signal, and LINT1

becomes NMI, a nonmaskable interrupt. INTR and NMI are backward

compatible with the signals of those names on the Celeron processor.

Both signals are asynchronous.

Both of these signals must be software configured via BIOS

programming of the APIC register space to be used either as NMI/

INTR or LINT[1:0]. Because the APIC is enabled by default after

reset, operation of these pins as LINT[1:0] is the default

configuration.

LOCK#

Input/

Output

LOCK# indicates to the system that a transaction must occur

atomically. This signal must connect the appropriate pins of both FSB

agents. For a locked sequence of transactions, LOCK# is asserted

from the beginning of the first transaction to the end of the last

transaction.

When the priority agent asserts BPRI# to arbitrate for ownership of

the FSB, it will wait until it observes LOCK# deasserted. This enables

symmetric agents to retain ownership of the FSB throughout the bus

locked operation and ensure the atomicity of lock.

PRDY#

Output

Probe Ready signal used by debug tools to determine processor

debug readiness.

PREQ#

Input

Probe Request signal used by debug tools to request debug operation

of the processor.

PROCHOT#

Output

PROCHOT# (Processor Hot) will go active when the processor

temperature monitoring sensor detects that the processor has

reached its maximum safe operating temperature. This indicates that

the processor Thermal Control Circuit has been activated, if enabled.

See Chapter 5 for more details.

PSI#

Output

Processor Power Status Indicator (PSI) signal. This signal is asserted

when the processor is in a lower state (Deep Sleep). See

Section 2.1.4 for more details.

Table 16.

Signal Description (Sheet 5 of 8)

Name

Type

Description

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