L9803 datasheet(54/126 Pages) STMICROELECTRONICS

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On-Chip Peripherals

L9803

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Bit 7 = ICIE Input Capture Interrupt Enable.

Interrupt is inhibited.

A timer interrupt is generated whenever the ICF1 or ICF2 bits of the SR register are set

Bit 6 = OCIE Output Compare Interrupt Enable.

Interrupt is inhibited.

A timer interrupt is generated whenever the OCF1 or OCF2 bits of the SR register are

set

Bit 5 = TOIE Timer Overflow Interrupt Enable.

Interrupt is inhibited.

A timer interrupt is enabled whenever the TOF bit of the SR register is set.

Bit 4 = FOLV2 Forced Output Compare 2.

No effect.

Forces the OLVL2 bit to be copied to the OCMP2 pin.

Bit 3 = FOLV1 Forced Output Compare 1.

No effect.

Forces OLVL1 to be copied to the OCMP1 pin.

Bit 2 = OLVL2 Output Level 2.

This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the

OCR2 register. This value is copied to the OCMP1 pin in One Pulse Mode and Pulse Width

Modulation mode.

Bit 1 = IEDG1 Input Edge 1.

This bit determines which type of level transition on the ICAP1 pin will trigger the capture.

A falling edge triggers the capture.

A rising edge triggers the capture.

Bit 0 = OLVL1 Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin whenever a successful comparison occurs with

the OCR1 register.

CONTROL REGISTER 2 (CR2)

Timer1 Register Address: 0031h

Timer2 Register Address: 0041h

L9803 데이터시트(PDF) 54 Page - STMicroelectronics