L9803 datasheet(49/126 Pages) STMICROELECTRONICS

49 / 126 page

L9803

On-Chip Peripherals

49/126

The following procedure is recommended to prevent the OCFi bit from being set between

the time it is read and the write to the OCiR register:

–

Write to the OCiHR register (further compares are inhibited).

–

Read the SR register (first step of the clearance of the OCFi bit, which may be

already set).

–

Write to the OCiLR register (enables the output compare function and clears the

OCFi bit).

Figure 25.

Output Compare Block Diagram

Figure 26.

Output Compare Timing Diagram, Internal Clock Divided by 2

Forced Compare Output capability

When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit

has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit=1). The

OCFi bit is then not set by hardware, and thus no interrupt request is generated.

FOLVLi bits have no effect in either One-Pulse mode or PWM mode.

OUTPUT COMPARE

16-bit

CIRCUIT

OC1R Register

16 BIT FREE RUNNING

COUNTER

OC1E

CC0

CC1

OC2E

OLVL1

OLVL2

OCIE

(Control Register 1) CR1

(Control Register 2) CR2

OCF2

OCF1

(Status Register) SR

16-bit

OCMP1

OCMP2

Latch

OC2R Register

FOLV2 FOLV1

INTERNAL CPU CLOCK

TIMER CLOCK

COUNTER

OUTPUT COMPARE REGISTER

COMPARE REGISTER LATCH

OCFi AND OCMPi PIN (OLVLi=1)

CPU

writes FFFF

FFFF

FFFD

FFFD FFFE FFFF 0000

FFFC

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