L9803 datasheet(81/126 Pages) STMICROELECTRONICS

81 / 126 page

L9803

On-Chip Peripherals

81/126

As a safeguard against programming errors, the configuration of the Bit Timing Register

(BTR) is only possible while the device is in STANDBY mode.

Figure 41.

Bit Timing

5.6.4

The CAN registers are organized as 6 general purpose registers plus 5 pages of 16

registers spanning the same address space and primarily used for message and filter

storage. The page actually selected is defined by the content of the Page Selection

General Purpose Registers

INTERRUPT STATUS REGISTER (ISR)

Read/Write

Reset Value: 00h

Bit 7 = RXIF3 Receive Interrupt Flag for Buffer 3

− Read/Clear

Set by hardware to signal that a new error-free message is available in buffer 3.

Cleared by software to release buffer 3.

Also cleared by resetting bit RDY of BCSR3.

Bit 6 = RXIF2 Receive Interrupt Flag for Buffer 2

− Read/Clear

Set by hardware to signal that a new error-free message is available in buffer 2.

Cleared by software to release buffer 2.

Also cleared by resetting bit RDY of BCSR2.

Bit 5 = RXIF1 Receive Interrupt Flag for Buffer 1

− Read/Clear

Set by hardware to signal that a new error-free message is available in buffer 1.

Cleared by software to release buffer 1.

Also cleared by resetting bit RDY of BCSR1.

Bit 4 = TXIF Transmit Interrupt Flag

− Read/Clear

Set by hardware to signal that the highest priority message queued for transmission has

been successfully transmitted (ETX = 0) or that it has passed successfully the arbitration

SYNC_SEG

BIT SEGMENT 1 (BS1)

BIT SEGMENT 2 (BS2)

NOMINAL BIT TIME

1 x tCAN

tBS1

tBS2

SAMPLE POINT

TRANSMIT POINT

RXIF3

RXIF2

RXIF1

TXIF

SCIF

ORIF

TEIF

EPND

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