L9803 datasheet(61/126 Pages) STMICROELECTRONICS

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L9803

On-Chip Peripherals

61/126

5.3

PWM Generator

5.3.1

Introduction

This PWM peripheral includes a 16-bit Pulse Width Modulator (PWM) and a programmable

prescaler able to generate an internal clock with period as long as 128*T

CPU.

The repetition rate of the 16-Bit PWM output can be defined by a dedicated register

(fCPU/CYREG); its resolution is defined by the internal clock as per the prescaler

programming.

Main Features

–

Programmable prescaler: fCPU divided by 2, 4, 8, 16, 32, 64 or 128.

–

1 control register

–

2 dedicated 16-bit registers for cycle and duty control

–

1 dedicated maskable interrupt

Procedure

To use the pulse width modulation peripheral, the EN_PWM bit in CONREG register must

be set.

Load PS(2:0) in CONREG register to define the programmable prescaler.

Load the CYREG register with the value defining the cycle length (in internal clock periods).

The 16 bits of this register are separated in two registers: CYREGH and CYREGL.

Timer1: 3E

Timer2: 4E

OCHR2

Reset Value

MSB

------

LSB

Timer1: 3F

Timer2: 4F

OCLR2

Reset Value

MSB

------

LSB

Timer1: 38

Timer2: 48

CHR

Reset Value

MSB

1111111

LSB

Timer1: 39

Timer2: 49

CLR

Reset Value

MSB

1111110

LSB

Timer1: 3A

Timer2: 4A

ACHR

Reset Value

MSB

1111111

LSB

Timer1: 3B

Timer2: 4B

ACLR

Reset Value

MSB

1111110

LSB

Timer1: 3C

Timer2: 4C

ICHR2

Reset Value

MSB

------

LSB

Timer1: 3D

Timer2: 4D

ICLR2

Reset Value

MSB

------

LSB

Table 10.

16-Bit Timer Register Map and Reset Values (continued)

Address

(Hex.)

Name

76543210

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