ADSP-BF504 datasheet(33/80 Pages) AD

33 / 80 page

Preliminary Technical Data

Rev. PrC

Page 33 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Parallel Peripheral Interface Timing

Table 25 and Figure 12 on Page 33, Figure 18 on Page 39, and

Figure 20 on Page 40 describe parallel peripheral interface

operations.

Table 25. Parallel Peripheral Interface Timing

Parameter

DDEXT = 1.8 V

DDEXT = 2.5/3.3 V

Min

Max

Min

Max

Unit

Timing Requirements

tPCLKW

PPI_CLK Width1

6.4

tPCLK

PPI_CLK Period1

Timing Requirements - GP Input and Frame Capture Modes

tSFSPE

External Frame Sync Setup Before PPI_CLK

(Nonsampling Edge for Rx, Sampling Edge for Tx)

6.7

tHFSPE

External Frame Sync Hold After PPI_CLK

1.0

tSDRPE

Receive Data Setup Before PPI_CLK

3.5

tHDRPE

Receive Data Hold After PPI_CLK

1.5

Switching Characteristics - GP Output and Frame Capture Modes

tDFSPE

Internal Frame Sync Delay After PPI_CLK

9.8

8.8

tHOFSPE

Internal Frame Sync Hold After PPI_CLK

1.7

tDDTPE

Transmit Data Delay After PPI_CLK

9.8

8.8

tHDTPE

Transmit Data Hold After PPI_CLK

1.8

1 PPI_CLK frequency cannot exceed fSCLK/2

Figure 12. PPI GP Rx Mode with External Frame Sync Timing

tPCLK

tSFSPE

POLS = 0

POLS = 1

DATA0 IS

SAMPLED

DATA1 IS

SAMPLED

PPI_DATA

POLC = 0

PPI_CLK

POLC = 1

PPI_CLK

PPI_FS1

PPI_FS2

tHFSPE

tHDRPE

tSDRPE

tPCLKW

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