ADSP-BF504 datasheet(26/80 Pages) AD

26 / 80 page

Rev. PrC

Page 26 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

ADSP-BF50x Clock Related Operating Conditions

Table 14 describes the core clock timing requirements for the

ADSP-BF50x processors. Take care in selecting MSEL, SSEL,

and CSEL ratios so as not to exceed the maximum core clock

and system clock (see Table 16). Table 15 describes phase-

locked loop operating conditions.

Table 14. Core Clock (CCLK) Requirements—ADSP-BF50x Processors—All Speed Grades1

Parameter

Maximum

Unit

fCCLK

Core Clock Frequency (VDDINT =tbd V Minimum)

400

MHz

fCCLK

Core Clock Frequency (VDDINT =tbd V Minimum)

TBD

MHz

fCCLK

Core Clock Frequency (VDDINT = tbd V Minimum)

TBD

MHz

fCCLK

Core Clock Frequency (VDDINT = tbd V Minimum)

TBD

MHz

fCCLK

Core Clock Frequency (VDDINT = tbd V Minimum)

TBD

MHz

1 See the Ordering Guide on Page 79.

Table 15. Phase-Locked Loop Operating Conditions

Parameter

Minimum

Maximum

Unit

fVCO

Voltage Controlled Oscillator (VCO) Frequency

Speed Grade

MHz

1 See the Ordering Guide on Page 79.

Table 16. Maximum SCLK Conditions for ADSP-BF50x Processors

Parameter

VDDEXT = 1.8 V/2.5 V/3.3 V Nominal Unit

SCLK

CLKOUT/SCLK Frequency (V

DDINT

≥ tbd V)

100

MHz

SCLK

CLKOUT/SCLK Frequency (V

DDINT

< tbd V)

TBD

MHz

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