ADSP-BF504 datasheet(42/80 Pages) AD

42 / 80 page

Rev. PrC

Page 42 of 80

January 2010

ADSP-BF504/F,ADSP-BF506F

Preliminary Technical Data

Serial Peripheral Interface (SPI) Port—Slave Timing

Table 33 and Figure 22 describe SPI port slave operations.

Table 33. Serial Peripheral Interface (SPI) Port—Slave Timing

Parameter

DDEXT = 1.8 V

DDEXT = 2.5/3.3 V

Min

Max

Min

Max

Unit

Timing Requirements

tSPICHS

Serial Clock High Period

2 × tSCLK –1.5

tSPICLS

Serial Clock Low Period

2 × tSCLK –1.5

tSPICLK

Serial Clock Period

4 × tSCLK

tHDS

Last SCK Edge to SPISS Not Asserted

2 × tSCLK –1.5

tSPITDS

Sequential Transfer Delay

2 × tSCLK –1.5

tSDSCI

SPISS Assertion to First SCK Edge

2 × tSCLK –1.5

tSSPID

Data Input Valid to SCK Edge (Data Input Setup)

1.6

tHSPID

SCK Sampling Edge to Data Input Invalid

1.6

Switching Characteristics

tDSOE

SPISS Assertion to Data Out Active

12.0

tDSDHI

SPISS Deassertion to Data High Impedance

8.5

tDDSPID

SCK Edge to Data Out Valid (Data Out Delay)

tHDSPID

SCK Edge to Data Out Invalid (Data Out Hold)

Figure 22. Serial Peripheral Interface (SPI) Port—Slave Timing

tSPICHS

tSPICLS

tSPICLK

tHDS

tSPITDS

tSDSCI

tSPICLS

tSPICHS

tDSOE

tDDSPID

tDSDHI

tHDSPID

MSB VALID

LSB VALID

MSB VALID

tSSPID

LSB

MSB

tDSDHI

tHDSPID

tDSOE

tHSPID

tSSPID

tDDSPID

LSB VALID

SPISS

(INPUT)

SCKx

(CPOL = 0)

(INPUT)

SCKx

(CPOL = 1)

(INPUT)

MISOx

(OUTPUT)

MOSIx

(INPUT)

MISOx

(OUTPUT)

MOSIx

(INPUT)

CPHA = 1

CPHA = 0

tHSPID

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