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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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FX980 데이터시트(PDF) 79 Page - CML Microcircuits |
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FX980 데이터시트(HTML) 79 Page - CML Microcircuits |
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79 / 86 page  TETRA Baseband Processor FX980 © 1997 Consumer Microcircuits Limited 79 D/980/3 1.7.1. Electrical Performance Timing Diagrams The following timings are provisional: 1.7.1.1 Serial Ports Timing Parameter Marker Min Max Units MCLK to SClk out - low to high t cslh 15 50 ns MCLK to SClk out - high to low t cshl 10 35 ns CmdDat set-up to falling edge of SClk t sis 35 ns CmdFS set-up to falling edge of SClk t sis 35 ns CmdDat hold from fall edge of SClk t sih 0 ns CmdFS hold from fall edge of SClk t sih 0 ns RxDat propagation from rising edge of SClk t sop 5 ns RxFS propagation from rising edge of SClk t sop 5 ns CmdRdDat propagation from rising edge of SClk t sop 5 ns CmdRdFS propagation from rising edge of SClk t sop 5 ns RxDat hold from rising edge of SClk t soh -5 ns RxFS hold from rising edge of SClk t soh -5 ns CmdRdDat hold from rising edge of SClk t soh -5 ns CmdRdFS hold from rising edge of SClk t soh -5 ns **Cmd port in Bi-dir mode ** CmdDat propagation from rising edge of SClk t sop 7 ns CmdDat hold from rising edge of SClk t soh -7 ns Figure 4 Serial Port Interfaces - Timing Parameters |
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