FX980 datasheet(20/86 Pages) CMLMICRO

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TETRA Baseband Processor

FX980

D/980/3

ConfigCtrl2

Title:

Configuration Control register

Address:

$0x01

Function:

Description:

General configuration bits, together with operational control signal bits.

Bit

Name

Active State

Function

Reserved. Set this bit Low. Undefined on read.

User defined bit. This bit has no internal functionality and

is reset Low with the global N_RESET pin. The user may

employ this bit for any useful purpose.

n_SlowDown

Low

When active, this bit reduces the slew rate of digital output

pins. This reduces power consumption, ground bounce and

reflection problems associated with fast edges on poorly

terminated lines. De-activation speeds up the digital

outputs, but increases power consumption, ground bounce

and reflection problems. It is anticipated that the latter

mode will be used only in 3.3V systems.

SRamIoRdInc

High

This bit determines whether a read or write operation to the

Auxiliary SRAM will increment the address pointers. When

set active causes read operations to move the address

pointer on, this would therefore allow an efficient write then

read verify scheme to be used. When set inactive write

operations increment the address pointer.

SRamloEn

High

When set active allows read/write access to the Auxiliary

SRAM. It is only valid to activate this bit when the SRAM is

not being accessed by the RamDac. When this bit is set

active, the first access to SramData will access the first

SRAM address location. Subsequent read or write

accesses will increment the address pointer to the next

memory location.

CoeffRamIoRdInc

High

This bit determines whether a read or write operation to a

coefficient memory will increment the address pointers.

When set active the address pointer is incremented by any

coefficient ram read operation, thereby allowing a write

then read verification. When set inactive, write operations

increment the address pointer.

CoeffRamloEn

High

When set active allows read/write access to all the

coefficient memories. This bit is valid only when the Tx and

Rx Data paths are inactive. When this bit is set active, the

first access to any of the coefficient memories will access

the first coefficient location (A1). Subsequent read or write

accesses to any coefficient memory will increment the

address pointers for all the coefficient memories.

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