| 전자부품 데이터시트 검색엔진 |
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MMA685X 데이터시트(PDF) 40 Page - Freescale Semiconductor, Inc |
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MMA685X 데이터시트(HTML) 40 Page - Freescale Semiconductor, Inc |
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40 / 52 page ![]() Sensors 40 Freescale Semiconductor, Inc. MMA685x 3.9 Serial Peripheral Interface MMA685x includes a Serial Peripheral Interface (SPI) to provide access to the configuration registers and digital data. Refer- ence Section 4 for details regarding the SPI protocol and available commands. 3.10 Device Initialization Following power-up, under-voltage reset, or a SPI reset command sequence, MMA685x proceeds through an internal initial- ization process as shown in Figure 31. Figure 31 also shows the MMA685x performance for an example external system level initialization procedure. Figure 31. Initialization Process Dly POR OTP Copy to Mirror Registers Offset Cancellation Startup Phase 2 Initialize R/W Registers to Desired State Verify Offset Verify Self Test & ARM Asserted Offset Cancellation Startup Phase 1 Offset Cancellation Startup Phase 3 Offset Cancellation Normal Mode Ready for SPI Command ENDINIT Clear Dly Re-Initialize R/W Registers (if needed) Activate Self Test Internal Offset Error Corrected to ‘0’ DeActivate Self Test Normal Mode Internal Initialization External Initialization Delay DeAssertion Dependent on Pulse Stretch and/or Arming Mode Assertion Dependent on Arming Mode Set ENDINIT Read DEVSTAT to clear flags Re-read DEVSTAT to verify Status tST_OMB tOC_PHASE1 tOC_PHASE2 tOC_PHASE3 tOP and ST ARM Notes:1) Self Test can be enabled and evaluated simultaneously to reduce test time. For failure mode coverage of the arming pins and of potential common axis failures, Freescale recommends independent self test activation. tSTRISE 2) tSTRISE and tSTFALL are dependent on the selected LPF group delay. Verify Offset & ARM DeAsserted Dly |
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