Sensors

16

Freescale Semiconductor, Inc.

MMA685x

3.1.7.3

Low-Pass Filter Selection Bits (LPF[3:0])

The Low Pass Filter selection bit selects a low-pass filter as shown in Table 11. Refer to Section 3.8.3 for details regarding

filter configurations.

Note: Filter characteristics do not include g-cell frequency response.

3.1.8

Arming Configuration Registers (ARMCFG)

The arming configuration register contains configuration information for the arming function. The values in this register are only

relevant if the arming function is operating in moving average mode, or count mode.

This register can be written during initialization but is locked once the ENDINIT bit is set. Refer to Section 3.1.6.2. This register

is included in the writable register CRC check. Refer to Section 3.2.2 for details.

3.1.8.1

Reserved Bits (Reserved)

Bits 7 through 6 of the ARMCFG register are reserved. A write to the reserved bits must always be logic ‘0’ for normal device

operation and performance.

Table 11. Low Pass Filter Selection Bits

LPF[3]

LPF[2]

LPF[1]

LPF[0]

Low Pass Filter Selected Nominal Sample Rate (

μs)

0

0

0

0

100 Hz, 4-pole

8

0

0

0

1

300 Hz, 4-Pole

8

0

0

1

0

400 Hz, 4-Pole

8

0

0

1

1

800 Hz, 4-Pole

8

0

1

0

0

1000 Hz, 4-Pole

8

0

1

0

1

400 Hz, 3-Pole

8

0

1

1

0

Reserved

Reserved

0

1

1

1

Reserved

Reserved

1

0

0

0

50 Hz, 4-Pole

16

1

0

0

1

150 Hz, 4-Pole

16

1

0

1

0

200 Hz, 4-Pole

16

1

0

1

1

400 Hz, 4-Pole

16

1

1

0

0

500 Hz, 4-Pole

16

1

1

0

1

200 Hz, 3-Pole

16

1

1

1

0

Reserved

Reserved

1

1

1

1

Reserved

Reserved

Table 12. Arming Configuration Register

Location

Bit

Address

Register

7

6543210

$0E

ARMCFG

Reserved

Reserved

APS[1]

APS[0]

AWS_N[1]

AWS_N[0]

AWS_P[1]

AWS_P[0]

Reset Value

0

0001111