CXD3003 datasheet(96/137 Pages) SONY

96 / 137 page

– 96 –

CXD3003R

• VC AVRG

The offset can be canceled by measuring the VC level which is the center voltage for the system and using

that value to apply compensation to each input error signal.

• FE AVRG

The FE signal DC level is measured. In addition, compensation is applied to the FZC comparator level output

from the SENS pin during FCS SEARCH (focus search) using these measurement results.

• TE AVRG

The TE signal DC level is measured.

• RF AVRG

The MIRR, DFCT and FOK signals are generated from the RF signal. Since the FOK signal is generated by

comparing the RF signal at a certain level, it is necessary to establish a zero level which becomes the

comparator level reference. Therefore, the RF signal is measured before playback, and is compensated to

take this level as the zero level.

An example of sending AVRG measurement and compensation commands is shown below.

(Example)

$380800 (RF AVRG measurement on)

$382000 (FE AVRG measurement on)

$380010 (TE AVRG measurement on)

$388000 (VC AVRG measurement on)

(Complete each AVRG measurement before starting the next.)

$38140A (RFLC, FLC0, FLC1 and TLC1 commands on)

(The required compensation should be turned on together; see Fig. 5-3.)

An interval of 5.8ms (when MCK = 128Fs) or more must be maintained between each command, or the SENS

pin must be monitored to confirm that the previous command has been completed before the next AVRG

command is sent.

See Fig. 5-3 for the contents of each compensation below.

• RFLC

The difference by which the RF signal exceeds the RF AVRG value is input to the RF In register.

(00 is input when the RF signal is lower than the RF AVRG value.)

• TCL0

The value obtained by subtracting the VC AVRG value from the TE signal is input to the TRK In register.

• TCL1

The value obtained by subtracting the TE AVRG value from the TE signal is input to the TRK In register.

• VCLC

The value obtained by subtracting the VC AVRG value from the FE signal is input to the FCS In register.

• FLC1

The value obtained by subtracting the FE AVRG value from the FE signal is input to the FCS In register.

• FLC0

The value obtained by subtracting the FE AVRG value from the FE signal is input to the FZC register.

CXD3003 데이터시트(PDF) 96 Page - Sony Corporation