 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
ST10F280 데이터시트(PDF) 228 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST10F280 데이터시트(HTML) 228 Page - STMicroelectronics |
|
|
228 / 239 page  Electrical characteristics ST10F280 228/239 Doc ID 8673 Rev. 3 t34 CC CLKOUT rising edge to ALE falling edge -2 + tA 8 + tA -2 + tA 8 + tA ns t35 SR Synchronous READY setup time to CLKOUT 12.5 – 12.5 – ns t36 SR Synchronous READY hold time after CLKOUT 2– 2 – ns t37 SR Asynchronous READY low time 35 – 2 TCL + 10 – ns t58 SR Asynchronous READY setup time (1) 12.5 – 12.5 – ns t59 SR Asynchronous READY hold time (1) 2– 2 – ns t60 SR Asynchronous READY hold time after RD, WR high (Demultiplexed Bus)(2) 0 0 + 2tA + tC + tF (2) 0 TCL - 12.5 + 2tA + tC + tF (2) ns 1. These timings are given for test purposes only, in order to assure recognition at a specific clock edge. 2. Demultiplexed bus is the worst case. For multiplexed bus 2 TCL are to be added to the maximum values. This adds even more time for deactivating READY. The 2tA and tC refer to the next following bus cycle, tF refers to the current bus cycle. Table 50. CLKOUT and READY characteristics (continued) Symbol Parameter Maximum CPU Clock = 40MHz Variable CPU Clock 1/2 TCL = 1 to 40MHz Min. Max. Min. Max. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
