전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

Preview PDF HTML

ST10F280 데이터시트(PDF) 229 Page - STMicroelectronics

부품명 ST10F280
상세설명  16-bit MCU with MAC unit, 512 Kbyte Flash memory and 18 Kbyte RAM
PDF  239 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  STMICROELECTRONICS [STMicroelectronics]
홈페이지  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

ST10F280 데이터시트(HTML) 229 Page - STMicroelectronics

Back Button ST10F280_12 Datasheet HTML 225Page - STMicroelectronics ST10F280_12 Datasheet HTML 226Page - STMicroelectronics ST10F280_12 Datasheet HTML 227Page - STMicroelectronics ST10F280_12 Datasheet HTML 228Page - STMicroelectronics ST10F280_12 Datasheet HTML 229Page - STMicroelectronics ST10F280_12 Datasheet HTML 230Page - STMicroelectronics ST10F280_12 Datasheet HTML 231Page - STMicroelectronics ST10F280_12 Datasheet HTML 232Page - STMicroelectronics ST10F280_12 Datasheet HTML 233Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 229 / 239 page
background image
ST10F280
Electrical characteristics
Doc ID 8673 Rev. 3
229/239
Figure 88.
CLKOUT and READY
1.
Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2.
The leading edge of the respective command depends on R/W-delay.
3.
READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled
LOW at this sampling point terminates the currently running bus cycle.
4.
READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
WR).
5.
If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to
CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t37 in order to be safely synchronized. This is
guaranteed, if READY is removed in response to the command (see Note 4)).
6.
Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state
may be inserted here.
For a multiplexed bus with MTTC wait state this delay is 2 CLKOUT cycles, for a demultiplexed bus without
MTTC wait state this delay is zero.
7.
The next external bus cycle may start here.
20.4.13
External bus arbitration
VDD = 5 V ± 10%, VSS = 0 V, TA = -40°C to 125°C, CL = 50 pF
t30
t34
t35
t36
t35
t36
t58
t59
t58
t59
wait state
READY
MUX / Tri-state 6)
t32
t33
t29
Running cycle 1)
t31
t37
3)
3)
5)
t60 4)
6)
2)
7)
3)
3)
CLKOUT
ALE
RD, WR
Synchronous
Asynchronous
READY
READY
GAPGCFT00942
Table 51.
External bus arbitration
Symbol
Parameter
Maximum CPU Clock
= 40MHz
Variable CPU Clock
1/2 TCL = 1 to 40MHz
Min.
Max.
Min.
Max.
t61
SR
HOLD input setup time to
CLKOUT
15
–
15
–
ns
t62
CC
CLKOUT to HLDA high or
BREQ low delay
–
12.5
–
12.5
ns
t63
CC
CLKOUT to HLDA low or
BREQ high delay
–
12.5
–
12.5
ns



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com