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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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SPEAR300 데이터시트(PDF) 12 Page - STMicroelectronics |
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SPEAR300 데이터시트(HTML) 12 Page - STMicroelectronics |
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12 / 83 page  Architecture overview SPEAr300 12/83 Doc ID 16324 Rev 2 2.2 System controller The System Controller provides an interface for controlling the operation of the overall system. Main features: ● Power saving system mode control ● Crystal oscillator and PLL control ● Configuration of system response to interrupts ● Reset status capture and soft reset generation ● Watchdog and timer module clock enable ● Remap control ● General purpose peripheral control r ● System and peripheral clock control and status 2.2.1 Clock and reset system The clock system is a fully programmable block that generates all the clocks for the SPEAr300. The default operating clock frequencies are: ● CPU_CLK @ 333 MHz for the CPU. ● HCLK @ 166 MHz for AHB bus and AHB peripherals. ● PCLK @ 83 MHz for, APB bus and APB peripherals. ● DDR_CLK @ 100-333 MHz for DDR memory interface. The above frequencies are the maximum allowed values. The clock frequencies can be modified by programming the clock system registers. The clock system consists of 2 main parts: a multi clock generator block and two internal PLLs. |
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