WM9093ECSSLASHR datasheet(49/84 Pages) WOLFSON

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Production Data

WM9093

PD, March 2012, Rev 4.2

CHARGE PUMP

The WM9093 incorporates a dual-mode Charge Pump which generates the supply rails for the

headphone output drivers, HPOUT1L and HPOUT1R. The Charge Pump has a single supply input,

HPVDD, and generates split rails CPVDD and CPVSS according to the selected mode of operation.

The Charge Pump connections are illustrated in Figure 15 (see “Electrical Characteristics” for external

component values). An input decoupling capacitor may also be required at HPVDD, depending upon

the system configuration.

HPVDD

WM9093

Charge Pump

CPVDD

CPVSS

GND

Figure 15 Charge Pump External Connections

The Charge Pump is enabled by setting the CP_ENA bit. When enabled, the charge pump adjusts the

output voltages (CPVDD and CPVSS) as well as the switching frequency in order to optimise the

power consumption according to the operating conditions.

The Charge Pump mode of operation is selected automatically according to the HPOUT1L_VOL and

HPOUT1R_VOL register settings.

Under the recommended usage conditions of the WM9093, the Charge Pump will be enabled by

running the default headphone Start-Up sequence as described in the “Control Write Sequencer”

section. (Similarly, it will be disabled by running the Shut-Down sequence.) In these cases, the user

does not need to write to the CP_ENA bit.

Note that the charge pump clock is derived from internal clock CLK_SYS which must be enabled by

setting OSC_ENA (see “Clocking Control”). The clock division from CLK_SYS is handled

transparently by the WM9093 without user intervention.

The CP_ENA register bit is defined in Table 27.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R76 (4Ch)

Charge Pump

CP_ENA

Charge Pump Control

0 = Disabled

1 = Enabled

Table 27 Charge Pump Control

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