WM8952ECSSLASHRV datasheet(43/72 Pages) WOLFSON

43 / 72 page

Pre Production

WM8952

PP, Rev 3.1, June 2011

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Clock

generation

control

CLKSEL

Controls the source of the clock for all

internal operation:

0=MCLK

1=PLL output

7:5

MCLKDIV

010

Sets the scaling for either the MCLK or

PLL clock output (under control of

CLKSEL)

000=divide by 1

001=divide by 1.5

010=divide by 2

011=divide by 3

100=divide by 4

101=divide by 6

110=divide by 8

111=divide by 12

4:2

BCLKDIV

000

Configures the BCLK and FRAME output

frequency, for use when the chip is

master over BCLK.

000=divide by 1 (BCLK=MCLK)

001=divide by 2 (BCLK=MCLK/2)

010=divide by 4

011=divide by 8

100=divide by 16

101=divide by 32

110=reserved

111=reserved

Sets the chip to be master over FRAME

and BCLK

0=BCLK and FRAME clock are inputs

1=BCLK and FRAME clock are outputs

generated by the WM8952 (MASTER)

Table 30 Clock Control

AUDIO SAMPLE RATES

The WM8952 sample rates are set using the SR register bits. The cut-offs for the digital filters and

the ALC attack/decay times stated are determined using these values and assume a 256fs master

clock rate.

If a sample rate that is not explicitly supported by the SR register settings is required then the

closest SR value to that sample rate should be chosen, the filter characteristics and the ALC attack,

decay and hold times will scale appropriately.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Additional

control

3:1

000

Approximate sample rate (configures the

coefficients for the internal digital filters):

000=48kHz

001=32kHz

010=24kHz

011=16kHz

100=12kHz

101=8kHz

110-111=reserved

Table 31 Sample Rate Control

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