Data Sheet

ADRF6806

Rev. B | Page 3 of 36

SPECIFICATIONS

differential RF input port impedance, all register and PLL settings use the recommended values shown in the Register Structure section,

unless otherwise noted.

Table 1.

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

FREQUENCY RANGE

50

525

MHz

RF INPUT @ 140 MHz

RFIP, RFIN pins

Input Return Loss

Relative to 100 Ω

−11.7

dB

Input P1dB

LPEN = 0 (standard power mode)

12.2

dBm

LPEN = 1 (low power mode)

10.6

dBm

Second-Order Input Intercept (IIP2)

LPEN = 0; −5 dBm each tone

>65

dBm

LPEN = 1; −5 dBm each tone

>60

dBm

Third-Order Input Intercept (IIP3)

LPEN = 0; −5 dBm each tone

28.5

dBm

LPEN = 1; −5 dBm each tone

25.2

dBm

Noise Figure

Double sideband from RF to either I or Q output; LPEN = 0

12.2

dB

Double sideband from RF to either I or Q output; LPEN = 1

11.4

dB

With a −5 dBm interferer 5 MHz away

14

dB

LO-to-RF Leakage

At 1×LO frequency, 100 Ω termination at the RF port

−70

dBm

I/Q BASEBAND OUTPUTS

IBBP, IBBN, QBBP, QBBN pins

Voltage Conversion Gain

450 Ω differential load across IBBP, IBBN (or QBBP, QBBN);

LPEN = 0

1

dB

450 Ω differential load across IBBP, IBBN (or QBBP, QBBN);

LPEN = 1

4.2

dB

Demodulation Bandwidth

1 V p-p signal 3 dB bandwidth; LPEN = 0

170

MHz

1 V p-p signal 3 dB bandwidth; LPEN = 1

135

MHz

Quadrature Phase Error

0.3

Degrees

I/Q Amplitude Imbalance

0.05

dB

Output DC Offset (Differential)

±8

mV

Output Common-Mode Reference

VOCM applied input voltage

1.55

1.65

1.75

V

Common-Mode Offset

25

mV

Gain Flatness

Any 5 MHz

0.2

dB p-p

Maximum Output Swing

Differential 450 Ω load

3

V p-p

Differential 200 Ω load

2.4

V p-p

Maximum Output Current

Each pin

6

mA p-p

LO INPUT/OUTPUT

LOP, LON

Output Level (LPEN = 0)

Into a differential 50 Ω load, LO buffer enabled (output

frequency = 800 MHz)

1

dBm

Output Level (LPEN = 1)

Into a differential 50 Ω load, LO buffer enabled (output

frequency = 800 MHz)

−0.75

dBm

Input Level

Externally applied 2×LO, PLL disabled

0

dBm

Input Impedance

Externally applied 2×LO, PLL disabled

50

Ω

LO Main Divider Range

VCO to mixer, including quadrature divider, see Table 5 for

supported divider modes

8

80

VCO Output Divider Range

VCO to (LOP, LON), see Table 6 for supported output divider

modes

4

8

VCO Operating Frequency

2800

4200

MHz

SYNTHESIZER SPECIFICATIONS

All synthesizer specifications measured with recommended

settings provided in Figure 33 through Figure 40

Channel Spacing

25

kHz

PLL Bandwidth

Can be adjusted with off-chip loop filter component values

67

kHz