M68ICS08GR datasheet(251/408 Pages) FREESCALE

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Serial Communications Interface (SCI)

SCI During Break Module Interrupts

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Serial Communications Interface (SCI)

251

18.7 SCI During Break Module Interrupts

The system integration module (SIM) controls whether status bits in

other modules can be cleared during the break state. The BCFE bit in

the SIM break flag control register (SBFCR) enables software to clear

status bits during the break state.

To allow software to clear status bits during a break interrupt, write a

logic 1 to the BCFE bit. If a status bit is cleared during the break state, it

remains cleared when the MCU exits the break state.

To protect status bits during the break state, write a logic 0 to the BCFE

bit. With BCFE at logic 0 (its default state), software can read and write

I/O registers during the break state without affecting status bits. Some

status bits have a 2-step read/write clearing procedure. If software does

the first step on such a bit before the break, the bit cannot change during

the break state as long as BCFE is at logic 0. After the break, doing the

second step clears the status bit.

18.8 I/O Signals

Port E shares two of its pins with the SCI module. The two SCI I/O pins

are:

•

PE2/TxD — Transmit data

•

PE1/RxD — Receive data

18.8.1 PE2/TxD (Transmit Data)

The PE2/TxD pin is the serial data output from the SCI transmitter. The

SCI shares the PE2/TxD pin with port E. When the SCI is enabled, the

PE2/TxD pin is an output regardless of the state of the DDRE0 bit in data

direction register E (DDRE).

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