M68ICS08GR datasheet(295/408 Pages) FREESCALE

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System Integration Module (SIM)

Technical Data

MC68HC908GR8 — Rev 4.0

295

System Integration Module (SIM)

MOTOROLA

19.8.2 SIM Reset Status Register

This register contains six flags that show the source of the last reset

provided all previous reset status bits have been cleared. Clear the SIM

reset status register by reading it. A power-on reset sets the POR bit and

clears all other bits in the register.

POR — Power-On Reset Bit

1 = Last reset caused by POR circuit

0 = Read of SRSR

PIN — External Reset Bit

1 = Last reset caused by external reset pin (RST)

0 = POR or read of SRSR

COP — Computer Operating Properly Reset Bit

1 = Last reset caused by COP counter

0 = POR or read of SRSR

ILOP — Illegal Opcode Reset Bit

1 = Last reset caused by an illegal opcode

0 = POR or read of SRSR

DEC

HIBYTE,SP

;Else deal with high byte, too.

DOLO

DEC

LOBYTE,SP

;Point to WAIT/STOP opcode.

RETURN

PULH

RTI

;Restore H register.

Address:

$FE01

Bit 7

654321

Bit 0

Read:

POR

COP

ILOP

ILAD

MODRST

LVI

Write:

Reset:

10000000

= Unimplemented

Figure 19-21. SIM Reset Status Register (SRSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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