M68ICS08GR datasheet(296/408 Pages) FREESCALE

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System Integration Module (SIM)

Technical Data

MC68HC908GR8 — Rev 4.0

296

System Integration Module (SIM)

MOTOROLA

ILAD — Illegal Address Reset Bit (opcode fetches only)

1 = Last reset caused by an opcode fetch from an illegal address

0 = POR or read of SRSR

MODRST — Monitor Mode Entry Module Reset Bit

1 = Last reset caused by monitor mode entry when vector locations

$FFFE and $FFFF are $00 after POR while IRQ = VDD

0 = POR or read of SRSR

LVI — Low-Voltage Inhibit Reset Bit

1 = Last reset caused by the LVI circuit

0 = POR or read of SRSR

19.8.3 SIM Break Flag Control Register

The SIM break control register contains a bit that enables software to

clear status bits while the MCU is in a break state.

BCFE — Break Clear Flag Enable Bit

This read/write bit enables software to clear status bits by accessing

status registers while the MCU is in a break state. To clear status bits

during the break state, the BCFE bit must be set.

1 = Status bits clearable during break

0 = Status bits not clearable during break

Address:

$FE03

Bit 7

654321

Bit 0

Read:

BCFE

RRRRRRR

Write:

Reset:

R= Reserved

Figure 19-22. SIM Break Flag Control Register (SBFCR)

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M68ICS08GR 데이터시트(PDF) 296 Page - Freescale Semiconductor, Inc