M68ICS08GR datasheet(355/408 Pages) FREESCALE

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Timer Interface Module (TIM)

I/O Registers

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Timer Interface Module (TIM)

355

22.10.5 TIM Channel Status and Control Registers

Each of the TIM channel status and control registers:

•

Flags input captures and output compares

•

Enables input capture and output compare interrupts

•

Selects input capture, output compare, or PWM operation

•

Selects high, low, or toggling output on output compare

•

Selects rising edge, falling edge, or any edge as the active input

capture trigger

•

Selects output toggling on TIM overflow

•

Selects 0% and 100% PWM duty cycle

•

Selects buffered or unbuffered output compare/PWM operation

Address: T1SC0, $0025 and T2SC0, $0030

Bit 7

654321

Bit 0

Read:

CH0F

CH0IE

MS0B

MS0A

ELS0B

ELS0A

TOV0

CH0MAX

Write:

Reset:

00000000

Figure 22-11. TIM Channel 0 Status and Control Register (TSC0)

Address: T1SC1, $0028

Bit 7

654321

Bit 0

Read:

CH1F

CH1IE

MS1A

ELS1B

ELS1A

TOV1

CH1MAX

Write:

Reset:

00000000

Figure 22-12. TIM Channel 1 Status and Control Register (TSC1)

Freescale Semiconductor, Inc.

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