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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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M68ICS08GR 데이터시트(PDF) 357 Page - Freescale Semiconductor, Inc |
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M68ICS08GR 데이터시트(HTML) 357 Page - Freescale Semiconductor, Inc |
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357 / 408 page  Timer Interface Module (TIM) I/O Registers MC68HC908GR8 — Rev 4.0 Technical Data MOTOROLA Timer Interface Module (TIM) 357 0 = Input capture operation When ELSxB:A = 00, this read/write bit selects the initial output level of the TCHx pin. See Table 22-3. Reset clears the MSxA bit. 1 = Initial output level low 0 = Initial output level high NOTE: Before changing a channel function by writing to the MSxB or MSxA bit, set the TSTOP and TRST bits in the TIM status and control register (TSC). ELSxB and ELSxA — Edge/Level Select Bits When channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. When channel x is an output compare channel, ELSxB and ELSxA control the channel x output behavior when an output compare occurs. When ELSxB and ELSxA are both clear, channel x is not connected to port D, and pin PTDx/TCHx is available as a general-purpose I/O pin. Table 22-3 shows how ELSxB and ELSxA work. Reset clears the ELSxB and ELSxA bits. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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