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FDC37C78-HT 데이터시트(PDF) 64 Page - Microchip Technology

부품명 FDC37C78-HT
상세설명  Floppy Disk Controller
PDF  82 Pages
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제조업체  MICROCHIP [Microchip Technology]
홈페이지  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

FDC37C78-HT 데이터시트(HTML) 64 Page - Microchip Technology

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Table 33 - Configuration Registers
Default
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
28H
CR00
Valid
Reserved
OSC
Reserved
FDC PWR
PDEN
Reserved
90H
CR01
Lock CRx
Reserved
Reserved
Reserved
Reserved
00H
CR02
Reserved
Reserved
Reserved
Reserved
70H
CR03
Reserved
IDENT
MFM
DRVDEN 1
Reserved
Reserved
Enhanced
FDC Mode 2
Reserved
00H
CR04
Reserved
00H
CR05
Reserved
EXTx4
DRV 0X1
DEN SEL
DMA Mode
Reserved
FFH
CR06
Floppy Drive D
Floppy Drive C
Floppy Drive B
Floppy Drive A
00H
CR07
Auto Power Management
Media ID Polarity
Floppy Boot Drive
00H
CR08
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
00H
CR09
Reserved
Reserved
Reserved
Reserved
Reserved
00H
CR0A
Reserved
Reserved
00H
CR0B
FDD3-DRTx
FDD2-DRTx
FDD1-DRTx
FDD0-DRTx
00H
CR0C
Reserved
78H
CR0D
Device ID/ 78H
00H
CR0E
Device Revision/00
00H
CR0F
Test
Test
Test
Test
Test
Test
Test
Test
00H
CR10
Test
Test
Test
Test
Test
Test
Test
Test
00H
CR11
Test
Test
Test
Test
Test
Test
Test
Test
00H
CR12-
CR1E
Reserved
00H
CR1F
FDD3-DTx
FDD2-DTx
FDD1-DTx
FDD0-DTx
Configuration Register Description
The
configuration
registers
consist
of
the
Configuration
Select
Register
(CSR)
and
Configuration Registers CR00 - CR1F. The
configuration select register is written to by writing
to port +0.
The Configuration Registers CR00;
CR1F are accessed by reading or writing to port
+1.
Configuration Select Register (CSR)
This register can only be accessed when the
chip is in the Configuration Mode. This register,
located at
port
+0, must be initialized upon
entering the Configuration Mode
before the configuration
registers
can be
accessed and is used to select which of the
Configuration Registers are to be accessed at port
+1.
Configuration Registers CR00 -CR1F
These registers are set to their default values at
power up and are not affected by RESET (except
where explicitly defined that a hardware reset
causes that bit to be reset to default). They are
accessed at port +1.
Refer to the following
descriptions for the function of each configuration
register.



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