FDC37C78-HT datasheet(19/82 Pages) MICROCHIP

19 / 82 page

DATA REGISTER (FIFO)

Address 3F5 READ/WRITE

All command parameter information, disk data and

result status are transferred between the host

processor and the floppy disk controller through

the Data Register.

Data transfers are governed by the RQM and DIO

bits in the Main Status Register.

The Data Register defaults to FIFO disabled mode

after any form of reset.

This maintains PC/AT

hardware compatibility. The default values can be

changed through the Configure command (enable

full FIFO operation with threshold control).

The

advantage of the FIFO is that it allows the system

a larger DMA latency without causing a disk error.

Table 15 gives several examples of the delays

with a

FIFO.

The data is based upon the following

formula:

At the start of a command, the FIFO action is

always disabled and command parameters must

be sent based upon the RQM and DIO bit settings.

As the command execution phase is entered, the

FIFO is cleared of any data to ensure that invalid

data is not transferred.

An overrun or underrun will terminate the current

command and the transfer of data. Disk writes will

complete the current sector by generating a 00

pattern and valid CRC. Reads require the host to

remove the remaining data so that the result

phase may be entered.

Table 13- FIFO Service Delay

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING AT

2 Mbps* DATA RATE

1 byte

2 bytes

8 bytes

15 bytes

1 x 4 µs - 1.5 µs = 2.5 µs

2 x 4 µs - 1.5 µs = 6.5 µs

8 x 4 µs - 1.5 µs = 30.5 µs

15 x 4 µs - 1.5 µs = 58.5 µs

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING AT

1 Mbps DATA RATE

1 byte

2 bytes

8 bytes

15 bytes

1 x 8 µs - 1.5 µs = 6.5 µs

2 x 8 µs - 1.5 µs = 14.5 µs

8 x 8 µs - 1.5 µs = 62.5 µs

15 x 8 µs - 1.5 µs = 118.5 µs

FIFO THRESHOLD

EXAMPLES

MAXIMUM DELAY TO SERVICING AT

500 Kbps DATA RATE

1 byte

2 bytes

8 bytes

15 bytes

1 x 16 µs - 1.5 µs = 14.5 µs

2 x 16 µs - 1.5 µs = 30.5 µs

8 x 16 µs - 1.5 µs = 126.5 µs

15 x 16 µs - 1.5 µs = 238.5 µs

*The 2 Mbps data rate is only available if VCC = 5V.

Threshold # x

DATA RATE

x 8

- 1.5 µs = DELAY

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