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FDC37C78-HT 데이터시트(PDF) 77 Page - Microchip Technology |
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FDC37C78-HT 데이터시트(HTML) 77 Page - Microchip Technology |
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77 / 82 page ![]() 77 FIGURE 5 - DMA TIMING nDACK Delay Time from DRQ High DRQ Reset Delay from nIOR or nIOW DRQ Reset Delay from nDACK Low nDACK Width nIOR Delay from DRQ High nIOW Delay from DRQ High Data Access Time from nIOR Low Data Set Up Time to nIOW High Data to Float Delay from nIOR High Data Hold Time from nIOW High nDACK Set Up to nIOW/nIOR Low nDACK Hold After nIOW/nIOR High TC Pulse Width nCS Set Up to nIOR/nIOW nCS Hold from nDACK TC Active to DRQ Inactive Parameter min typ max units t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 0 150 0 0 40 10 10 5 10 60 40 10 100 100 100 60 100 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t15 t2 t3 t12 t16 t1 t4 t5 t6 t11 t14 t8 t7 t9 t10 t13 nCS DRQ, nDACK nIOR or nIOW DATA (DO-D7) TC DATA VALID |
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