| 전자부품 데이터시트 검색엔진 |
|
AM85C30 데이터시트(PDF) 27 Page - Advanced Micro Devices |
|
|
|||||||||||||||||||||||||||||
AM85C30 데이터시트(HTML) 27 Page - Advanced Micro Devices |
|
27 / 194 page ![]() System Interface AMD 2–9 Table 2–3. Enhancement Options WR15 bit D2 WR15 D0 WR7 ′ bit D6 10x19-bit SDLC/HDLC Extended FIFO Enabled Enhance Enabled Read Enable Functions Enabled 1 0 x 10x19-bit FIFO enhancement enabled only 0 1 0 SDLC/HDLC enhancements enabled only 0 1 1 SDLC/HDLC enhancements enabled with extended read enabled 1 1 0 10x19-bit FIFO and SDLC/ HDLC enhancements enabled 1 1 1 10x19-bit FIFO and SDLC/ HDLC enhancements with extended read enabled Bit D0 of WR15 determines whether or not other enhancements pertinent only to SDLC/ HDLC Mode operation are available for programming via WR7 ′ as shown below. Write Register 7 prime (WR7 ′ ) can be written to when bit D0 of WR15 is set to ‘1’. When this bit is set, writing to WR7 (flag register) actually writes to WR7 ′. If bit D6 of this register is set to ‘1’, previously unreadable registers WR3, WR4, WR5, WR10 are readable by the processor. In addition, WR7 ′ is also readable by having this bit set. WR3 is read when a bogus RR9 register is accessed during a read cycle, WR10 is read by accessing RR11, and WR7 ′ is accessed by executing a read to RR14. The Am85C30 register map with bit D0 of WR15 and bit D6 of WR7 ′ set is shown in Table 2–5. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |