AM85C30 datasheet(90/194 Pages) AMD

90 / 194 page

Data Communication Modes Functional Description

AMD

4–38

Receive Data FIFO

Receive Shift Register

Eight Bit Time Delay

CRC Checker

Receive Data

Figure 4–24. Receive CRC Data Path for Synchronous Mode

4.10.2.2.1

Tx CRC Initialization

The initial state of the transmit and receive CRC generators is controlled by bit D7 of

WR10. When this bit is set to ‘1’, both generators will be preset to an initial value of all

‘1’s, if this bit is set to ‘0’, both generators will be reset to ‘0’s. The SCC does not auto-

matically preset the transmit CRC generator, so this must be done in software. This is

accomplished by issuing the Reset Tx CRC Generator command, which is encoded in

bits D7 and D6 of WR0. For proper results this command must be issued while the trans-

mitter is enabled and sending sync characters.

4.10.2.2.2

Tx CRC Enabling

If CRC is to be used, the transmit CRC generator must be enabled by setting bit D0 of

WR5 to ‘1’. This bit may also be used to exclude certain characters from the CRC calcula-

tion in Synchronous modes.

4.10.2.2.3

CRC Transmission

As in SDLC mode, the transmission of the CRC check characters in Synchronous modes

is controlled by the Transmit CRC Enable bit in WR5 (D0) and Tx Underrun/EOM bit in

RR0 (D6). If the Transmit Enable bit is set to ‘0’ when a transmit underrun occurs, the

CRC check characters will not be sent regardless of the state of the Tx Underrun/EOM

bit. If the Transmit Enable bit is set to ‘1’ when a transmit underrun occurs then the state

of the Tx Underrun/EOM bit determines the action taken by the transmitter. The Tx Un-

derrun/EOM bit is set by the transmitter and only reset by the processor via the Reset Tx

Underrun/EOM command in WR0.

If the Tx Underrun/EOM bit is set to ‘1’ when an underrun occurs, the transmitter will

close the message just sent by sending sync characters; however, if this bit is set to ‘0’,

the transmitter will close the message by sending the accumulated CRC followed by sync

characters. The transmitter will idle the transmission line by sending sync characters until

either more data are written to the Transmit Buffer or the transmitter is disabled.

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