AM85C30 datasheet(17/194 Pages) AMD

17 / 194 page

General Information

AMD

1–9

1.5.2

Serial Channel Pin Descriptions

CTSA, CTSB — Clear to Send (inputs, active Low)

If the Auto Enable bit in WR3 (D5) is set, a Low on these inputs enables the respective

transmitter; otherwise they may be used as general-purpose inputs. Both inputs are

Schmitt-trigger buffered to accommodate slow rise-time inputs. The SCC detects transi-

tions on these inputs and, depending on whether or not other External/Status Interrupts

are pending, can interrupt the processor on either logic level transitions.

DCDA, DCDB — Data Carrier Detect (inputs, active Low)

These pins function as receiver enables if the Auto Enable bit in WR3 (D5) is set; other-

wise they may be used as general-purpose input pins. Both pins are Schmitt-trigger buff-

ered to accommodate slow rise-time signals. The SCC detects transitions on these inputs

and, depending on whether or not other External/Status Interrupts are pending, can inter-

rupt the processor on either logic level transitions.

DTR/REQA, DTR/REQB — Data Terminal Ready/Request (outputs, active Low)

These pins function as DMA requests for the transmitter if bit D2 of WR14 is set; other-

wise they may be used as general-purpose outputs following the state programmed into

the DTR bit.

PCLK — Clock (input)

This is the master clock used to synchronize internal signals. PCLK is not required to

have any phase relationship with the master system clock.

RTSA, RTSB — Request to Send (outputs, active Low)

When the Request to Send (RTS) bit in WR5 is set, the

RTS pin goes Low. When the

RTS bit is reset in the Asynchronous mode and the Auto Enable bit in WR3 (D5) is set,

the signal goes High after the transmitter is empty. In Synchronous mode or Asynchro-

nous mode with the Auto Enable bit reset, the

RTS pins strictly follow the state of the RTS

bits. Both pins can be used as general-purpose outputs. Request to send outputs are not

affected by the state of the Auto Enable (D5) bit in WR3 in synchronous mode.

RTxCA, RTxCB — Receive/Transmit Clocks (inputs, active Low)

The functions of these pins are under program control. In each channel,

RTxC may sup-

ply the receive clock, the transmit clock, the clock for the baud rate generator, or the clock

for the digital phase-locked loop. These pins can also be programmed for use with the

respective

SYNC pins as a crystal oscillator. The receive clock may be 1, 16, 32, or 64

times the data rate in Asynchronous mode.

If a clock is supplied on these pins in NRZI or NRZ mode serial data on the RxD pin will

be sampled on the rising edge of these pins. In FM mode, RxD is sampled on both clock

edges.

RxDA, RxDB — Receive Data (inputs, active High)

Serial data is received through these pins.

SYNCA, SYNCB — Synchronization (inputs/outputs, active Low)

These pins can act as either inputs, outputs, or as part of the crystal oscillator circuit. In

the Asynchronous mode (crystal oscillator option not selected), these pins are inputs simi-

lar to

CTS and DCD. In this mode, transitions on these lines affect the state of the SYNC/

HUNT status bit in Read Register 0, but have no other function.

In External Synchronization mode, with the crystal oscillator not selected, these lines also

act as inputs. In this mode, SYNC must be driven Low two receive clock cycles after the

last bit of the sync character is received. Character assembly begins on the rising edge of

the receive clock immediately following the activation of SYNC.

In the Internal Synchronization mode (Monosync and Bisync), with the crystal oscillator

not selected, these pins act as outputs and are active only during the part of the receive

clock cycle in which sync characters are recognized. The sync condition is not latched, so

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