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AM85C30 데이터시트(PDF) 131 Page - Advanced Micro Devices

부품명 AM85C30
상세설명  Serial Communications Controller
PDF  194 Pages
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제조업체  AMD [Advanced Micro Devices]
홈페이지  http://www.amd.com
Logo AMD - Advanced Micro Devices

AM85C30 데이터시트(HTML) 131 Page - Advanced Micro Devices

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Register Description
AMD
6–21
1
1
001
0
1
Transmit Clock
Data
NRZ
NRZI
FM1
FM0
Receive Clock
NRZ
1
1
001
0
1
Data
NRZI
FM1
FM0
Bit Cell
Bit Cell
Figure 6–12. NRZ (NRZI) FM1 (FM0) Timing
Bit 7: CRC Presets ‘1’ or ‘0’
This bit specifies the initialized condition of the receive CRC checker and the transmit
CRC generator. If this bit is set to ‘1’, the CRC generator and checker are preset to ‘1’. If
this bit is set to ‘0’, the CRC generator and checker are preset to ‘0’. Either option can be
selected with either CRC polynomial. In SDLC mode, the transmitted CRC is inverted be-
fore transmission and the received CRC is checked against the bit pattern
“0001110100001111.” This bit is reset by a channel or hardware reset. This bit is ignored
in Asynchronous mode.
Bits 6 and 5: Data Encoding 1 and 2
These bits control the coding method used for both the transmitter and the receiver, as
illustrated in Table 6–5. All of the clocking options are available for all coding methods.
The DPLL in the SCC is useful for recovering clocking information in NRZI and FM
modes. Any coding method can be used in the X1 mode. A hardware reset forces NRZ
mode. Timing for the various modes is shown in Figure 6–12.



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