MPC8347VRAGDB datasheet(38/99 Pages) FREESCALE

38 / 99 page

MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

Local Bus

Figure 20 provides the AC test load for the local bus.

Figure 20. Local Bus C Test Load

Table 39. Local Bus General Timing Parameters—DLL Bypass9

Parameter

Symbol1

Min

Max

Unit

Notes

Local bus cycle time

tLBK

—

Input setup to local bus clock

tLBIVKH

—

3, 4

Input hold from local bus clock

tLBIXKH

1.0

—

3, 4

LALE output fall to LAD output transition (LATCH hold time)

tLBOTOT1

1.5

—

LALE output fall to LAD output transition (LATCH hold time)

tLBOTOT2

3—

LALE output fall to LAD output transition (LATCH hold time)

tLBOTOT3

2.5

—

Local bus clock to output valid

tLBKLOV

—3

Local bus clock to output high impedance for LAD/LDP

tLBKHOZ

—4

Notes:

1. The symbols for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB)

for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock one

(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output

(O) going invalid (X) or output hold time.

2. All timings are in reference to the falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or the rising edge

of LCLK0 (for all other inputs).

3. All signals are measured from OVDD/2 of the rising/falling edge of LCLK0 to 0.4 × OVDD of the signal in question for 3.3 V

signaling levels.

4. Input timings are measured at the pin.

5. tLBOTOT1 should be used when RCWH[LALE] is set and when the load on the LALE output pin is at least 10 pF less than the

load on the LAD output pins.

6. tLBOTOT2 should be used when RCWH[LALE] is not set and when the load on the LALE output pin is at least 10 pF less than

the load on the LAD output pins.the

7. tLBOTOT3 should be used when RCWH[LALE] is not set and when the load on the LALE output pin equals to the load on the

LAD output pins.

8. For purposes of active/float timing measurements, the Hi-Z or off-state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

9. DLL bypass mode is not recommended for use at frequencies above 66 MHz.

Output

Z0 = 50 Ω

OVDD/2

RL = 50 Ω

MPC8347VRAGDB 데이터시트(PDF) 38 Page - Freescale Semiconductor, Inc

MPC8347VRAGDB 데이터시트(HTML) 38 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99

데이터시트 다운로드

링크 URL