MPC8347VRAGDB datasheet(98/99 Pages) FREESCALE

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MPC8347EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 12

Freescale Semiconductor

Document Revision History

8/2006

• Changed all references to revision 2.0 silicon to revision 3.0 silicon.

• Changed VIH minimum value in Table 39, “JTAG Interface DC Electrical Characteristics,” to

OVDD –0.3.

• In Table 40, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min

= 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.

• In Table 44, “PCI DC Electrical Characteristics,” changed high-level input voltage values to min

= 2 and max = OVDD + 0.3; changed low-level input voltage values to min = (–0.3) and max = 0.8.

• Updated DDR2 I/O power values in Table 5, “MPC8347EA Typical I/O Power Dissipation.”

• In Table 63, “Suggested PLL Configurations,” deleted reference-number rows 902 and 703.

4/2006

• Removed Table 20, “Timing Parameters for DDR2-400.”

• Changed ADDR/CMD to ADDR/CMD/MODT in Table 9, “DDR and DDR2 SDRAM Output AC

Timing Specifications,” rows 2 and 3, and in Figure 2, “DDR SDRAM Output Timing Diagram.

• Changed Min and Max values for VIH and VIL in Table 40,“PCI DC Electrical Characteristics.”

• In Table 51, “MPC8347EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout

Listing,” modified rows for MDICO and MDIC1 signals and added note ‘It is recommended that

MDICO be tied to GRD using an 18

Ω resistor and MCIC1 be tied to DDR power using an 18 Ω

resistor.’

• In Table 51, “MPC8347EA (TBGA) Pinout Listing,” and Table 52, “MPC8347EA (PBGA) Pinout

Listing,” in row AVDD3 changed power supply from “AVDD3” to ‘—.’

3/2006

Initial public release

Table 72. Document Revision History (continued)

Rev.

Number

Date

Substantive Change(s)

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