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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AT89LP51RB2 데이터시트(PDF) 32 Page - ATMEL Corporation |
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AT89LP51RB2 데이터시트(HTML) 32 Page - ATMEL Corporation |
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32 / 254 page  32 3722A–MICRO–10/11 AT89LP51RB2/RC2/IC2 Preliminary 5.2 Compatibility Mode Compatibility (12-Clock) mode is enabled by default from the factory or by setting the Compati- bility User Fuse. In Compatibility mode instruction bytes are fetched every three system clock cycles and the CPU operates with 6-state machine cycles and a divide-by-2 system clock for 12 oscillator periods per machine cycle. Standard instructions execute in1, 2 or 4 machine cycles. Instr u ction timing in th is mode is com p a t i b l e wit h st a nd a rd 8 051 s s u ch a s t h e AT89C51RB2/RC2/IC2. In Compatibility mode there is no difference in timing between instruc- tions executed from internal versus external program memory. Compatibility mode can be used to preserve the execution profiles of legacy applications. For a summary of differences between Fast and Compatibility modes see Table 2-3 on page 12. Examples of Compatibility mode instructions are shown in Figure 5-2. Figure 5-2. Instruction Execution Sequences in Compatibility Mode 5.3 Multiply–Accumulate Unit (MAC) The AT89LP51RB2/RC2/IC2 includes a multiply and accumulate (MAC) unit that can signifi- cantly speed up many mathematical operations required for digital signal processing. The MAC unit includes a 16-by-16 bit multiplier and a 40-bit adder that can perform integer or fractional multiply-accumulate operations on signed 16-bit input values. The MAC unit also includes a 1-bit arithmetic shifter that will left or right shift the contents of the 40-bit MAC accumulator register (M). S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 S2 S2 S3 S3 S4 S4 S5 S5 S6 S6 S1 S1 CLK CLK ALE ALE READ OPCODE READ OPCODE (A) 1-byte, 1-cycle instruction, e.g., INC A A (B) 2-byte, 1-cycle instruction, e.g., ADD A, #data (B) 2-byte, 1-cycle instruction, e.g., ADD A, #data (C) 1-byte, 2-cycle instruction, e.g., INC DPTR (C) 1-byte, 2-cycle instruction, e.g., INC DPTR (D) MOVX (1-byte, 2-cycle) (D) MOVX (1-byte, 2-cycle) READ NEXT READ NEXT OPCODE OPCODE (DISCARD) (DISCARD) READ NEXT OPCODE AGAIN READ NEXT OPCODE AGAIN READ OPCODE READ OPCODE READ 2ND READ 2ND BYTE BYTE READ NEXT OPCODE READ NEXT OPCODE READ OPCODE READ OPCODE READ NEXT READ NEXT OPCODE AGAIN OPCODE AGAIN READ READ OPCODE OPCODE (MOVX) (MOVX) NO NO ALE ALE READ NEXT READ NEXT OPCODE (DISCARD) OPCODE (DISCARD) READ NEXT READ NEXT OPCODE OPCODE AGAIN AGAIN NO NO FETCH FETCH DA DATA ACCESS EXTERNAL MEMOR ACCESS EXTERNAL MEMORY ADDR ADDR NO NO FETCH FETCH READ NEXT READ NEXT OPCODE (DISCARD) OPCODE (DISCARD) |
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