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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AT89LP51RB2 데이터시트(PDF) 38 Page - ATMEL Corporation |
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AT89LP51RB2 데이터시트(HTML) 38 Page - ATMEL Corporation |
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38 / 254 page  38 3722A–MICRO–10/11 AT89LP51RB2/RC2/IC2 Preliminary 5.4.2 Data Pointer Operating Modes The Dual Data Pointers on the AT89LP51RB2/RC2/IC2 include three additional operating modes that affect data pointer based instructions. These modes are controlled by bits in DSPR. Note that these bits in DSPR should be cleared to zero, disabling these modes, before any calls are made to the Flash API.Care must also be taken when interrupt routines use data pointers to ensure that correct operation is saved/restored correctly. 5.4.2.1 DPTR Redirect The Data Pointer Redirect to B bit, DPRB (DSPR.0), allows MOVX and MOVC instructions to use the B register as the data source/destination when the instruction references DPTR1 as shown in Table 5-8 and Table 5-9. DPRB can improve the efficiency of routines that must fetch multiple operands from different RAM locations. 5.4.2.2 Index Disable The MOVC Index Disable bit, MVCD (DSPR.1), disables the indexed addressing mode of the MOVC A, @A+DPTR instruction. When MVCD = 1, the MOVC instruction functions as MOVC A, @DPTR with no indexing as shown in Table 5-9. MVCD can improve the efficiency of routines that must fetch multiple operands from program memory. DPRB can change the MOVC destination register from ACC to B, but has no effect on the MOVC index register. Table 5-8. MOVX @DPTR Operating Modes DPRB DPS Equivalent Operation for MOVX MOVX A, @DPTR MOVX @DPTR, A DPTR /DPTR DPTR /DPTR 00 MOVX A, @DPTR0 MOVX A, @DPTR1 MOVX @DPTR0, A MOVX @DPTR1, A 01 MOVX A, @DPTR1 MOVX A, @DPTR0 MOVX @DPTR1, A MOVX @DPTR0, A 10 MOVX A, @DPTR0 MOVX B, @DPTR1 MOVX @DPTR0, A MOVX @DPTR1, B 11 MOVX B, @DPTR1 MOVX A, @DPTR0 MOVX @DPTR1, B MOVX @DPTR0, A Table 5-9. MOVC @DPTR Operating Modes MVCD DPRB Equivalent Operation for MOVC A, @A+DPTR DPS = 0 DPS = 1 DPTR /DPTR DPTR /DPTR 00 MOVC A, @A+DPTR0 MOVC A, @A+DPTR1 MOVC A, @A+DPTR1 MOVC A, @A+DPTR0 01 MOVC A, @A+DPTR0 MOVC B, @A+DPTR1 MOVC B, @A+DPTR1 MOVC A, @A+DPTR0 10 MOVC A, @DPTR0 MOVC A, @DPTR1 MOVC A, @DPTR1 MOVC A, @DPTR0 11 MOVC A, @DPTR0 MOVC B, @DPTR1 MOVC B, @DPTR1 MOVC A, @DPTR0 |
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