376 datasheet(41/95 Pages) INTEL

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376 EMBEDDED PROCESSOR

240182 – 19

Figure 44 Fastest Read Cycles with Non-Pipelined Timing

The fastest 80376 bus cycle requires only two bus

states For example three consecutive bus read cy-

cles each consisting of two bus states are shown

by Figure 44 The bus states in each cycle are

named T1 and T2 Any memory or IO address may

be accessed by such a two-state bus cycle if the

external hardware is fast enough

Every bus cycle continues until it is acknowledged

by the external system hardware using the 80376

READY input Acknowledging the bus cycle at the

end of the first T2 results in the shortest bus cycle

requiring only T1 and T2 If READY is not immedi-

ately asserted however T2 states are repeated in-

definitely until the READY input is sampled active

The pipelining option provides a choice of bus cycle

timings

Pipelined or non-pipelined cycles are

selectable on a cycle-by-cycle basis with the Next

Address (NA) input

When pipelining is selected the address (BHE BLE

and A23–A1) and definition (WR DC MIO and

LOCK) of the next cycle are available before the end

of the current cycle To signal their availability the

80376 address status output (ADS) is asserted Fig-

ure 45 illustrates the fastest read cycles with pipe-

lined timing

Note from Figure 45 the fastest bus cycles using

pipelining require only two bus states named T1P

and T2P Therefore pipelined cycles allow the same

data bandwidth as non-pipelined cycles but ad-

dress-to-data access time is increased by one

T-state time compared to that of a non-pipelined cy-

cle

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