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UM0434 데이터시트(PDF) 59 Page - STMicroelectronics |
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UM0434 데이터시트(HTML) 59 Page - STMicroelectronics |
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59 / 390 page ![]() Register model UM0434 60/391 protection violation exception and a byte-ordering exception. System software must check beyond ESR[BO], such as the state of MSR[PR] in SRR1 and the TLB entry page protection bits, to determine whether a protection violation also occurred. The ESR fields are described in Table 34. 4.9.1 VLE mode instruction syndrome ESR[VLEMI] indicates when an interrupt is caused by a VLE instruction. This syndrome bit is set on an exception associated with execution or attempted execution of a VLE instruction. This bit is updated for the interrupt types in Table 34. Table 34. ESR field descriptions Bits Name Description Associated interrupt type 32–35 — Reserved, should be cleared. — 36 PIL Illegal instruction exception Program 37 PPR Privileged instruction exception Program 38 PTR Trap exception Program 39 FP Floating-point operation Alignment, data storage, data TLB, program 40 ST Store operation Alignment, data storage, data TLB 41 — Reserved, should be cleared. — 42 DLK Data cache locking(1) Data storage 43 ILK Instruction cache locking Data storage` 44 AP Auxiliary processor operation. (unused in the e200z3) Alignment, data storage, data TLB, program 45 PUO Unimplemented operation exception Program 46 BO Byte ordering exception Data storage 47 PIE Program imprecise exception. Unused in the e200z3 (Reserved, should be cleared.) — 48–55 — Reserved, should be cleared. — 56 SPE SPE APU operation SPE unavailable, SPE floating-point data exception, SPE floating-point round exception, alignment, data storage, data TLB 57 — Reserved, should be cleared. — 58 VLEM I VLE mode instruction SPE unavailable, SPE floating-point data exception, SPE floating-point round exception, data storage, data TLB, instruction storage, alignment, program, and system call 59–61 — Reserved, should be cleared. — 62 MIF Misaligned instruction fetch Instruction storage, instruction TLB 63 XTE External termination error (precise) Data storage, instruction storage 1. When optional cache is present. Unused on e200z3. |
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