UM0434 datasheet(95/390 Pages) STMICROELECTRONICS

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The MAS6 register is shown in

Table 83.

MAS6 fields are defined in

Table 84.

4.16.5

Process ID register (PID0)

The process ID register, PID0, is shown in

Table 85. The Book E architecture requires that a

process ID (PID) value be associated with each effective address (instruction or data)

generated by the processor. Book E defines one PID register that maintains the value of the

PID for the current process. The number of PIDs implemented is indicated by the value of

44–47 TIDSELD

TID default selection value. 4-bit field that specifies which of the current PID registers should be

used to load the MAS1[TID] field on a TLB miss exception.

The PID registers are addressed as follows:

0000 = PID0 (PID).

0001 = PID1.

...

1110 = PID14.

A value that references a non-implemented PID register causes a value of 0 to be placed in

MAS1[TID].

48–51

—

Reserved, should be cleared.

52–55

TSIZED

Default TSIZE value.

56–57

—

Reserved, should be cleared.

VLED

Default VLE value. Specifies the default value loaded into MAS2[VLE] on a TLB miss

exception.

59–63 DWIMGE Default WIMGE values.

Table 82.

MAS4 - hardware replacement assist configuration register (continued)

Bits

Name

Description

Table 83.

MMU assist register 6 (MAS6))

39 40

47 48

62 63

Field

—

SPID

—

SAS

Reset

Undefined on

m_por assertion, unchanged on p_reset_b assertion

R/W

SPR

SPR 630

Table 84.

MAS6 - TLB search context register 0

Bits

Name

Description

32–39

—

Reserved, should be cleared.

40–47

SPID

PID value for searches

48–62

—

Reserved, should be cleared.

SAS

AS value for searches

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