UM0434 datasheet(44/390 Pages) STMICROELECTRONICS

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UM0434

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4.4.2

Processor ID register (PIR)

The processor ID for the CPU core is contained in the processor ID register (PIR), shown in

Figure 8. The contents of PIR reflect the hardware input signals to the e200z3 core.

PIR fields are described in

Table 9.

4.4.3

Processor version register (PVR)

The processor version register (PVR), shown in

Table 10, contains the processor version

number for the CPU core.

56–57

—

Reserved, should be cleared.

Instruction address space.

0 The processor directs all instruction fetches to address space 0 (TS = 0 in the

relevant TLB entry).

1 The processor directs all instruction fetches to address space 1 (TS = 1 in the

relevant TLB entry).

Data address space.

0 The core directs all data storage accesses to address space 0 (TS = 0 in the

relevant TLB entry).

1 The core directs all data storage accesses to address space 1 (TS = 1 in the

relevant TLB entry).

60–63

—

Reserved, should be cleared.

Table 7.

MSR field descriptions (continued)

Bits

Name

Description

Table 8.

Processor ID register (PIR)

Field

—

PID

Reset

0000_0000_0000_0000_0000_0000

p_cpuid[0:7]

R/W

Read only

SPR

SPR 286

Table 9.

PIR Field Descriptions

Bits

Name

Description

32–55

—

These bits always read as 0.

56–63

PID

These bit reflect the values on the

p_cpuid[0:7] input signals.

Table 10.

Processor version register (PVR)

36 37 38

43 44

47 48

55 56

59 60

Field

Manufacturer ID

—

Type

Version

MBG Use

Major Rev

MBG ID

Reset

1000

01_0001

0010

p_pvrin[16:31]

R/W

Read only

SPR

SPR 287

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